diff options
author | Jayachandran C <jayachandranc@netlogicmicro.com> | 2011-05-07 01:36:21 +0530 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2011-05-19 09:55:40 +0100 |
commit | efa0f81c11021c95b1e72c65868115b6fb4ecc6a (patch) | |
tree | 493e0d3db7107e3aafc66bb44f8d5df751395e33 /arch/mips/mm/tlbex.c | |
parent | 3c595a515dbb61ae96e8f5607d895820aa06e870 (diff) |
MIPS: Netlogic: Cache, TLB support and feature overrides for XLR
CPU_XLR case added to mm/tlbex.c
CPU_XLR case added to mm/c-r4k.c for PINDEX attribute
Feature overrides for XLR cpu.
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2333/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/tlbex.c')
-rw-r--r-- | arch/mips/mm/tlbex.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index f5734c2c809..424ed4b92e6 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -404,6 +404,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_5KC: case CPU_TX49XX: case CPU_PR4450: + case CPU_XLR: uasm_i_nop(p); tlbw(p); break; |