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authorLinus Torvalds <torvalds@linux-foundation.org>2008-10-11 09:19:02 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2008-10-11 09:19:02 -0700
commit835a1c092432b3293ba6c4dec45ee6869c6f61fd (patch)
treea48582e4e4de3a8924b700c5ccaae78cd299cd73 /arch/mips/include/asm/mach-ip27/war.h
parentd3570a5a7b8d0604fa012129f92637dc1534f62c (diff)
parent9609e74093abd9f61fb1d20a8915a8ea87c77d5a (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (49 commits) MIPS: RB532: provide GPIO_BUILTIN_NR and irq_to_gpio/gpio_to_irq MIPS: Move ptrace prototypes to ptrace.h MIPS: Ptrace support for HARDWARE_WATCHPOINTS MIPS: Scheduler support for HARDWARE_WATCHPOINTS. MIPS: Watch exception handling for HARDWARE_WATCHPOINTS. MIPS: Probe watch registers and report configuration. MIPS: Add HARDWARE_WATCHPOINTS definitions and support code. MIPS: Add HARDWARE_WATCHPOINTS configure option. MIPS: Replace use of <asm-generic/uaccess.h> with native implementations. MIPS: TXx9: Add TX4939 ATA support (v2) MIPS: Rewrite spinlocks to ticket locks. MIPS: IP checksums: Optimize adjust of sum on buffers of odd alignment. MIPS: IP checksums: Remove unncessary .set pseudos MIPS: IP checksums: Remove unncessary folding of sum to 16 bit. MIPS: Move headfiles to new location below arch/mips/include MIPS: Alchemy: rename directory MIPS: Optimize get_user and put_user for 64-bit MIPS: TXx9: Implement prom_free_prom_memory MIPS: TXx9: Add RBTX4939 board support MIPS: TXx9: Add TX4939 SoC support ...
Diffstat (limited to 'arch/mips/include/asm/mach-ip27/war.h')
-rw-r--r--arch/mips/include/asm/mach-ip27/war.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
new file mode 100644
index 00000000000..e2ddcc9b1ff
--- /dev/null
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_IP27_WAR_H
+#define __ASM_MIPS_MACH_IP27_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R4600_V2_HIT_CACHEOP_WAR 0
+#define R5432_CP0_INTERRUPT_WAR 0
+#define BCM1250_M3_WAR 0
+#define SIBYTE_1956_WAR 0
+#define MIPS4K_ICACHE_REFILL_WAR 0
+#define MIPS_CACHE_SYNC_WAR 0
+#define TX49XX_ICACHE_INDEX_INV_WAR 0
+#define RM9000_CDEX_SMP_WAR 0
+#define ICACHE_REFILLS_WORKAROUND_WAR 0
+#define R10000_LLSC_WAR 1
+#define MIPS34K_MISSED_ITLB_WAR 0
+
+#endif /* __ASM_MIPS_MACH_IP27_WAR_H */