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authorFlorian Fainelli <florian@openwrt.org>2011-11-16 19:11:12 +0100
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 22:03:04 +0000
commite1c96c8620539f056291fe42f742f331f5d291b1 (patch)
treebcb161d447e8029bf8be300254afbbc9e63af7c6 /arch/mips/include/asm/mach-bcm63xx
parentd61fcfe2bbb27d4da18c609cf279627ae1b74151 (diff)
MIPS: BCM63xx: Remove BCM6345 hacks to read base boot address
Though BCM6345 does not technically have the same MPI register layout than the other SoCs, reading the chip-select registers is done the same way, and particularly for chip-select 0, which is the boot flash. Signed-off-by: Florian Fainelli <florian@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-bcm63xx')
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 23403a32c15..5b8d15bb5fe 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -215,7 +215,7 @@ enum bcm63xx_regs_set {
#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
#define BCM_6345_ENETSW_BASE (0xdeadbeef)
#define BCM_6345_PCMCIA_BASE (0xfffe2028)
-#define BCM_6345_MPI_BASE (0xdeadbeef)
+#define BCM_6345_MPI_BASE (0xfffe2000)
#define BCM_6345_OHCI0_BASE (0xfffe2100)
#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)