diff options
| author | Manuel Lauss <manuel.lauss@googlemail.com> | 2011-08-02 19:51:03 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-10-24 23:34:23 +0100 |
| commit | ce1d43b9a9e8a3db8fe91696c0b0e3ac1a154e34 (patch) | |
| tree | 7e47005c61e98f44005c17a636457c4398c73fdd /arch/mips/alchemy | |
| parent | 2e8fd2e5efe6b7cebba0beec44c6c2f474c6b726 (diff) | |
MIPS: Alchemy: support multiple GPIO styles in one kernel
For GPIOLIB=y decide at runtime which gpiochips to register;
in the GPIOLIB=n case, the gpio headers need to be reshuffled
a bit to make multiple implementations coexist peacefully.
Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/2679/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/alchemy')
| -rw-r--r-- | arch/mips/alchemy/common/Makefile | 4 | ||||
| -rw-r--r-- | arch/mips/alchemy/common/gpiolib.c (renamed from arch/mips/alchemy/common/gpiolib-au1000.c) | 35 |
2 files changed, 22 insertions, 17 deletions
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index 27811fe341d..62f0d39e93c 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -12,9 +12,7 @@ obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o # optional gpiolib support ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) - ifeq ($(CONFIG_GPIOLIB),y) - obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o - endif + obj-$(CONFIG_GPIOLIB) += gpiolib.o endif obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib.c index c8e1a94d4a9..91fb4d9e30f 100644 --- a/arch/mips/alchemy/common/gpiolib-au1000.c +++ b/arch/mips/alchemy/common/gpiolib.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org> - * GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0. + * GPIOLIB support for Alchemy chips. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -23,18 +23,18 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. * * Notes : - * au1000 SoC have only one GPIO block : GPIO1 - * Au1100, Au15x0, Au12x0 have a second one : GPIO2 + * This file must ONLY be built when CONFIG_GPIOLIB=y and + * CONFIG_ALCHEMY_GPIO_INDIRECT=n, otherwise compilation will fail! + * au1000 SoC have only one GPIO block : GPIO1 + * Au1100, Au15x0, Au12x0 have a second one : GPIO2 */ +#include <linux/init.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/types.h> -#include <linux/platform_device.h> #include <linux/gpio.h> - -#include <asm/mach-au1x00/au1000.h> -#include <asm/mach-au1x00/gpio.h> +#include <asm/mach-au1x00/gpio-au1000.h> static int gpio2_get(struct gpio_chip *chip, unsigned offset) { @@ -115,12 +115,19 @@ struct gpio_chip alchemy_gpio_chip[] = { }, }; -static int __init alchemy_gpiolib_init(void) +static int __init alchemy_gpiochip_init(void) { - gpiochip_add(&alchemy_gpio_chip[0]); - if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000) - gpiochip_add(&alchemy_gpio_chip[1]); - - return 0; + int ret = 0; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + ret = gpiochip_add(&alchemy_gpio_chip[0]); + break; + case ALCHEMY_CPU_AU1500...ALCHEMY_CPU_AU1200: + ret = gpiochip_add(&alchemy_gpio_chip[0]); + ret |= gpiochip_add(&alchemy_gpio_chip[1]); + break; + } + return ret; } -arch_initcall(alchemy_gpiolib_init); +arch_initcall(alchemy_gpiochip_init); |