aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/alchemy/common/time.c
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2009-09-17 20:52:32 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-17 20:52:32 -0700
commit3dc95666df0e1ae5b7381a8ec97a583bb3ce4306 (patch)
treefc1b277f507c48b8c29536947e1de5c2eeda9325 /arch/mips/alchemy/common/time.c
parentb938fb6f491113880ebaabfa06c6446723c702fd (diff)
parent9b1fc55a05006523bced65f4d99f7072831ff56a (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (51 commits) MIPS: BCM63xx: Add integrated ethernet mac support. MIPS: BCM63xx: Add support for the Broadcom BCM63xx family of SOCs. MIPS: BCM63xx: Add Broadcom 63xx CPU definitions. MIPS: Octeon: Move some platform device registration to its own file. MIPS: Don't corrupt page tables on vmalloc fault. MIPS: Shrink the size of tlb handler MIPS: Alchemy: override loops_per_jiffy detection MIPS: hw_random: Add hardware RNG for Octeon SOCs. MIPS: Octeon: Add hardware RNG platform device. MIPS: Remove useless zero initializations. MIPS: Alchemy: get rid of allow_au1k_wait MIPS: Octeon: Set kernel_uses_llsc to false on non-SMP builds. MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC. MIPS: Get rid of CONFIG_CPU_HAS_LLSC MIPS: Malta: Remove pointless use use of CONFIG_CPU_HAS_LLSC MIPS: Rewrite clearing of ll_bit on context switch in C MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler MIPS: Consolidate all CONFIG_CPU_HAS_LLSC use in a single C file. MIPS: Clean up linker script using new linker script macros. MIPS: Use PAGE_SIZE in assembly instead of _PAGE_SIZE. ...
Diffstat (limited to 'arch/mips/alchemy/common/time.c')
-rw-r--r--arch/mips/alchemy/common/time.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 33fbae79af5..f34ff860194 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -36,14 +36,13 @@
#include <linux/interrupt.h>
#include <linux/spinlock.h>
+#include <asm/processor.h>
#include <asm/time.h>
#include <asm/mach-au1x00/au1000.h>
/* 32kHz clock enabled and detected */
#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
-extern int allow_au1k_wait; /* default off for CP0 Counter */
-
static cycle_t au1x_counter1_read(struct clocksource *cs)
{
return au_readl(SYS_RTCREAD);
@@ -153,13 +152,17 @@ void __init plat_time_init(void)
printk(KERN_INFO "Alchemy clocksource installed\n");
- /* can now use 'wait' */
- allow_au1k_wait = 1;
return;
cntr_err:
- /* counters unusable, use C0 counter */
+ /*
+ * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
+ * function is called. Because the Alchemy counters are unusable
+ * the C0 timekeeping code is installed and use of the 'wait'
+ * instruction must be prohibited, which is done most easily by
+ * assigning NULL to cpu_wait.
+ */
+ cpu_wait = NULL;
r4k_clockevent_init();
init_r4k_clocksource();
- allow_au1k_wait = 0;
}