diff options
| author | Peter Turczak <peter@turczak.de> | 2011-08-09 14:11:19 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-10-18 14:22:25 +1000 |
| commit | 89127ed381fb244aa51c1a74ed695a1f3578ef7d (patch) | |
| tree | 7c0f331b438cb1f56b73bd18e39766274d43cbe5 /arch/m68k/include/asm/mcfqspi.h | |
| parent | f230e80b423f6cb002015ab4771c06a53d5a2287 (diff) | |
m68knommu: fix problems with SPI/GPIO on ColdFire 520x
The problem has its root in the calculation of the set-port offsets (macro
MCFGPIO_SETR() in arch/m68k/include/asm/gpio.h), this assumes that all ports
have the same offset from the base port address (MCFGPIO_SETR) which is
defined in mcf520xsim.h as an alias of MCFGIO_PSETR_BUSCTL. Because the BUSCTL
and BE port do not have a set-register (see MCF5208 Reference Manual Page
13-10, Table 13-3) the offset calculations went wrong.
Because the BE and BUSCTL port do not seem useful in these parts, as they
lack a set register, I removed them and adapted the gpio chip bases which
are also used for the offset-calculations. Now both setting and resetting
the chip selects works as expected from userland and from the kernelspace.
Signed-off-by: Peter Turczak <peter@turczak.de>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/mcfqspi.h')
| -rw-r--r-- | arch/m68k/include/asm/mcfqspi.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h index 39d90d51111..7fe631972f1 100644 --- a/arch/m68k/include/asm/mcfqspi.h +++ b/arch/m68k/include/asm/mcfqspi.h @@ -24,9 +24,11 @@ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) #define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) #elif defined(CONFIG_M5249) -#define MCFQSPI_IOBASE (MCF_MBAR + 0x300) -#elif defined(CONFIG_M520x) || defined(CONFIG_M532x) -#define MCFQSPI_IOBASE 0xFC058000 +#define MCFQSPI_IOBASE (MCF_MBAR + 0x300) +#elif defined(CONFIG_M520x) +#define MCFQSPI_IOBASE 0xFC05C000 +#elif defined(CONFIG_M532x) +#define MCFQSPI_IOBASE 0xFC058000 #endif #define MCFQSPI_IOSIZE 0x40 |