Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

8 files changed, 63595 insertions, 0 deletions

diff --git a/arch/m68k/ifpsp060/src/README-SRC b/arch/m68k/ifpsp060/src/README-SRC
new file mode 100644
index 00000000000..6be5cff2a6a
--- /dev/null
+++ b/arch/m68k/ifpsp060/src/README-SRC
@@ -0,0 +1,12 @@
+This is the original source code from Motorola for the 68060 processor
+support code, providing emulation for rarely used m68k instructions
+not implemented in the 68060 silicon.
+
+The code provided here will not assemble out of the box using the GNU
+assembler, however it is being included in order to comply with the
+GNU General Public License.
+
+You don't need to actually assemble these files in order to compile a
+workin m68k kernel, the precompiled .sa files in arch/m68k/ifpsp060
+are sufficient and were generated from these source files by
+Motorola.
diff --git a/arch/m68k/ifpsp060/src/fplsp.S b/arch/m68k/ifpsp060/src/fplsp.S
new file mode 100644
index 00000000000..fdb79b927ef
--- /dev/null
+++ b/arch/m68k/ifpsp060/src/fplsp.S
@@ -0,0 +1,10980 @@
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
+M68000 Hi-Performance Microprocessor Division
+M68060 Software Package
+Production Release P1.00 -- October 10, 1994
+
+M68060 Software Package Copyright © 1993, 1994 Motorola Inc.  All rights reserved.
+
+THE SOFTWARE is provided on an "AS IS" basis and without warranty.
+To the maximum extent permitted by applicable law,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+and any warranty against infringement with regard to the SOFTWARE
+(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
+
+To the maximum extent permitted by applicable law,
+IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
+(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
+BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS)
+ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
+Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
+
+You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
+so long as this entire notice is retained without alteration in any modified and/or
+redistributed versions, and that such modified versions are clearly identified as such.
+No licenses are granted by implication, estoppel or otherwise under any patents
+or trademarks of Motorola, Inc.
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#
+# lfptop.s:
+#	This file is appended to the top of the 060ILSP package
+# and contains the entry points into the package. The user, in
+# effect, branches to one of the branch table entries located here.
+#
+
+	bra.l	_facoss_
+	short	0x0000
+	bra.l	_facosd_
+	short	0x0000
+	bra.l	_facosx_
+	short	0x0000
+
+	bra.l	_fasins_
+	short	0x0000
+	bra.l	_fasind_
+	short	0x0000
+	bra.l	_fasinx_
+	short	0x0000
+
+	bra.l	_fatans_
+	short	0x0000
+	bra.l	_fatand_
+	short	0x0000
+	bra.l	_fatanx_
+	short	0x0000
+
+	bra.l	_fatanhs_
+	short	0x0000
+	bra.l	_fatanhd_
+	short	0x0000
+	bra.l	_fatanhx_
+	short	0x0000
+
+	bra.l	_fcoss_
+	short	0x0000
+	bra.l	_fcosd_
+	short	0x0000
+	bra.l	_fcosx_
+	short	0x0000
+
+	bra.l	_fcoshs_
+	short	0x0000
+	bra.l	_fcoshd_
+	short	0x0000
+	bra.l	_fcoshx_
+	short	0x0000
+
+	bra.l	_fetoxs_
+	short	0x0000
+	bra.l	_fetoxd_
+	short	0x0000
+	bra.l	_fetoxx_
+	short	0x0000
+
+	bra.l	_fetoxm1s_
+	short	0x0000
+	bra.l	_fetoxm1d_
+	short	0x0000
+	bra.l	_fetoxm1x_
+	short	0x0000
+
+	bra.l	_fgetexps_
+	short	0x0000
+	bra.l	_fgetexpd_
+	short	0x0000
+	bra.l	_fgetexpx_
+	short	0x0000
+
+	bra.l	_fgetmans_
+	short	0x0000
+	bra.l	_fgetmand_
+	short	0x0000
+	bra.l	_fgetmanx_
+	short	0x0000
+
+	bra.l	_flog10s_
+	short	0x0000
+	bra.l	_flog10d_
+	short	0x0000
+	bra.l	_flog10x_
+	short	0x0000
+
+	bra.l	_flog2s_
+	short	0x0000
+	bra.l	_flog2d_
+	short	0x0000
+	bra.l	_flog2x_
+	short	0x0000
+
+	bra.l	_flogns_
+	short	0x0000
+	bra.l	_flognd_
+	short	0x0000
+	bra.l	_flognx_
+	short	0x0000
+
+	bra.l	_flognp1s_
+	short	0x0000
+	bra.l	_flognp1d_
+	short	0x0000
+	bra.l	_flognp1x_
+	short	0x0000
+
+	bra.l	_fmods_
+	short	0x0000
+	bra.l	_fmodd_
+	short	0x0000
+	bra.l	_fmodx_
+	short	0x0000
+
+	bra.l	_frems_
+	short	0x0000
+	bra.l	_fremd_
+	short	0x0000
+	bra.l	_fremx_
+	short	0x0000
+
+	bra.l	_fscales_
+	short	0x0000
+	bra.l	_fscaled_
+	short	0x0000
+	bra.l	_fscalex_
+	short	0x0000
+
+	bra.l	_fsins_
+	short	0x0000
+	bra.l	_fsind_
+	short	0x0000
+	bra.l	_fsinx_
+	short	0x0000
+
+	bra.l	_fsincoss_
+	short	0x0000
+	bra.l	_fsincosd_
+	short	0x0000
+	bra.l	_fsincosx_
+	short	0x0000
+
+	bra.l	_fsinhs_
+	short	0x0000
+	bra.l	_fsinhd_
+	short	0x0000
+	bra.l	_fsinhx_
+	short	0x0000
+
+	bra.l	_ftans_
+	short	0x0000
+	bra.l	_ftand_
+	short	0x0000
+	bra.l	_ftanx_
+	short	0x0000
+
+	bra.l	_ftanhs_
+	short	0x0000
+	bra.l	_ftanhd_
+	short	0x0000
+	bra.l	_ftanhx_
+	short	0x0000
+
+	bra.l	_ftentoxs_
+	short	0x0000
+	bra.l	_ftentoxd_
+	short	0x0000
+	bra.l	_ftentoxx_
+	short	0x0000
+
+	bra.l	_ftwotoxs_
+	short	0x0000
+	bra.l	_ftwotoxd_
+	short	0x0000
+	bra.l	_ftwotoxx_
+	short	0x0000
+
+	bra.l	_fabss_
+	short	0x0000
+	bra.l	_fabsd_
+	short	0x0000
+	bra.l	_fabsx_
+	short	0x0000
+
+	bra.l	_fadds_
+	short	0x0000
+	bra.l	_faddd_
+	short	0x0000
+	bra.l	_faddx_
+	short	0x0000
+
+	bra.l	_fdivs_
+	short	0x0000
+	bra.l	_fdivd_
+	short	0x0000
+	bra.l	_fdivx_
+	short	0x0000
+
+	bra.l	_fints_
+	short	0x0000
+	bra.l	_fintd_
+	short	0x0000
+	bra.l	_fintx_
+	short	0x0000
+
+	bra.l	_fintrzs_
+	short	0x0000
+	bra.l	_fintrzd_
+	short	0x0000
+	bra.l	_fintrzx_
+	short	0x0000
+
+	bra.l	_fmuls_
+	short	0x0000
+	bra.l	_fmuld_
+	short	0x0000
+	bra.l	_fmulx_
+	short	0x0000
+
+	bra.l	_fnegs_
+	short	0x0000
+	bra.l	_fnegd_
+	short	0x0000
+	bra.l	_fnegx_
+	short	0x0000
+
+	bra.l	_fsqrts_
+	short	0x0000
+	bra.l	_fsqrtd_
+	short	0x0000
+	bra.l	_fsqrtx_
+	short	0x0000
+
+	bra.l	_fsubs_
+	short	0x0000
+	bra.l	_fsubd_
+	short	0x0000
+	bra.l	_fsubx_
+	short	0x0000
+
+# leave room for future possible additions
+	align	0x400
+
+#
+# This file contains a set of define statements for constants
+# in order to promote readability within the corecode itself.
+#
+
+set LOCAL_SIZE,		192			# stack frame size(bytes)
+set LV,			-LOCAL_SIZE		# stack offset
+
+set EXC_SR,		0x4			# stack status register
+set EXC_PC,		0x6			# stack pc
+set EXC_VOFF,		0xa			# stacked vector offset
+set EXC_EA,		0xc			# stacked <ea>
+
+set EXC_FP,		0x0			# frame pointer
+
+set EXC_AREGS,		-68			# offset of all address regs
+set EXC_DREGS,		-100			# offset of all data regs
+set EXC_FPREGS,		-36			# offset of all fp regs
+
+set EXC_A7,		EXC_AREGS+(7*4)		# offset of saved a7
+set OLD_A7,		EXC_AREGS+(6*4)		# extra copy of saved a7
+set EXC_A6,		EXC_AREGS+(6*4)		# offset of saved a6
+set EXC_A5,		EXC_AREGS+(5*4)
+set EXC_A4,		EXC_AREGS+(4*4)
+set EXC_A3,		EXC_AREGS+(3*4)
+set EXC_A2,		EXC_AREGS+(2*4)
+set EXC_A1,		EXC_AREGS+(1*4)
+set EXC_A0,		EXC_AREGS+(0*4)
+set EXC_D7,		EXC_DREGS+(7*4)
+set EXC_D6,		EXC_DREGS+(6*4)
+set EXC_D5,		EXC_DREGS+(5*4)
+set EXC_D4,		EXC_DREGS+(4*4)
+set EXC_D3,		EXC_DREGS+(3*4)
+set EXC_D2,		EXC_DREGS+(2*4)
+set EXC_D1,		EXC_DREGS+(1*4)
+set EXC_D0,		EXC_DREGS+(0*4)
+
+set EXC_FP0,		EXC_FPREGS+(0*12)	# offset of saved fp0
+set EXC_FP1,		EXC_FPREGS+(1*12)	# offset of saved fp1
+set EXC_FP2,		EXC_FPREGS+(2*12)	# offset of saved fp2 (not used)
+
+set FP_SCR1,		LV+80			# fp scratch 1
+set FP_SCR1_EX,		FP_SCR1+0
+set FP_SCR1_SGN,	FP_SCR1+2
+set FP_SCR1_HI,		FP_SCR1+4
+set FP_SCR1_LO,		FP_SCR1+8
+
+set FP_SCR0,		LV+68			# fp scratch 0
+set FP_SCR0_EX,		FP_SCR0+0
+set FP_SCR0_SGN,	FP_SCR0+2
+set FP_SCR0_HI,		FP_SCR0+4
+set FP_SCR0_LO,		FP_SCR0+8
+
+set FP_DST,		LV+56			# fp destination operand
+set FP_DST_EX,		FP_DST+0
+set FP_DST_SGN,		FP_DST+2
+set FP_DST_HI,		FP_DST+4
+set FP_DST_LO,		FP_DST+8
+
+set FP_SRC,		LV+44			# fp source operand
+set FP_SRC_EX,		FP_SRC+0
+set FP_SRC_SGN,		FP_SRC+2
+set FP_SRC_HI,		FP_SRC+4
+set FP_SRC_LO,		FP_SRC+8
+
+set USER_FPIAR,		LV+40			# FP instr address register
+
+set USER_FPSR,		LV+36			# FP status register
+set FPSR_CC,		USER_FPSR+0		# FPSR condition codes
+set FPSR_QBYTE,		USER_FPSR+1		# FPSR qoutient byte
+set FPSR_EXCEPT,	USER_FPSR+2		# FPSR exception status byte
+set FPSR_AEXCEPT,	USER_FPSR+3		# FPSR accrued exception byte
+
+set USER_FPCR,		LV+32			# FP control register
+set FPCR_ENABLE,	USER_FPCR+2		# FPCR exception enable
+set FPCR_MODE,		USER_FPCR+3		# FPCR rounding mode control
+
+set L_SCR3,		LV+28			# integer scratch 3
+set L_SCR2,		LV+24			# integer scratch 2
+set L_SCR1,		LV+20			# integer scratch 1
+
+set STORE_FLG,		LV+19			# flag: operand store (ie. not fcmp/ftst)
+
+set EXC_TEMP2,		LV+24			# temporary space
+set EXC_TEMP,		LV+16			# temporary space
+
+set DTAG,		LV+15			# destination operand type
+set STAG,		LV+14			# source operand type
+
+set SPCOND_FLG,		LV+10			# flag: special case (see below)
+
+set EXC_CC,		LV+8			# saved condition codes
+set EXC_EXTWPTR,	LV+4			# saved current PC (active)
+set EXC_EXTWORD,	LV+2			# saved extension word
+set EXC_CMDREG,		LV+2			# saved extension word
+set EXC_OPWORD,		LV+0			# saved operation word
+
+################################
+
+# Helpful macros
+
+set FTEMP,		0			# offsets within an
+set FTEMP_EX,		0			# extended precision
+set FTEMP_SGN,		2			# value saved in memory.
+set FTEMP_HI,		4
+set FTEMP_LO,		8
+set FTEMP_GRS,		12
+
+set LOCAL,		0			# offsets within an
+set LOCAL_EX,		0			# extended precision
+set LOCAL_SGN,		2			# value saved in memory.
+set LOCAL_HI,		4
+set LOCAL_LO,		8
+set LOCAL_GRS,		12
+
+set DST,		0			# offsets within an
+set DST_EX,		0			# extended precision
+set DST_HI,		4			# value saved in memory.
+set DST_LO,		8
+
+set SRC,		0			# offsets within an
+set SRC_EX,		0			# extended precision
+set SRC_HI,		4			# value saved in memory.
+set SRC_LO,		8
+
+set SGL_LO,		0x3f81			# min sgl prec exponent
+set SGL_HI,		0x407e			# max sgl prec exponent
+set DBL_LO,		0x3c01			# min dbl prec exponent
+set DBL_HI,		0x43fe			# max dbl prec exponent
+set EXT_LO,		0x0			# min ext prec exponent
+set EXT_HI,		0x7ffe			# max ext prec exponent
+
+set EXT_BIAS,		0x3fff			# extended precision bias
+set SGL_BIAS,		0x007f			# single precision bias
+set DBL_BIAS,		0x03ff			# double precision bias
+
+set NORM,		0x00			# operand type for STAG/DTAG
+set ZERO,		0x01			# operand type for STAG/DTAG
+set INF,		0x02			# operand type for STAG/DTAG
+set QNAN,		0x03			# operand type for STAG/DTAG
+set DENORM,		0x04			# operand type for STAG/DTAG
+set SNAN,		0x05			# operand type for STAG/DTAG
+set UNNORM,		0x06			# operand type for STAG/DTAG
+
+##################
+# FPSR/FPCR bits #
+##################
+set neg_bit,		0x3			# negative result
+set z_bit,		0x2			# zero result
+set inf_bit,		0x1			# infinite result
+set nan_bit,		0x0			# NAN result
+
+set q_sn_bit,		0x7			# sign bit of quotient byte
+
+set bsun_bit,		7			# branch on unordered
+set snan_bit,		6			# signalling NAN
+set operr_bit,		5			# operand error
+set ovfl_bit,		4			# overflow
+set unfl_bit,		3			# underflow
+set dz_bit,		2			# divide by zero
+set inex2_bit,		1			# inexact result 2
+set inex1_bit,		0			# inexact result 1
+
+set aiop_bit,		7			# accrued inexact operation bit
+set aovfl_bit,		6			# accrued overflow bit
+set aunfl_bit,		5			# accrued underflow bit
+set adz_bit,		4			# accrued dz bit
+set ainex_bit,		3			# accrued inexact bit
+
+#############################
+# FPSR individual bit masks #
+#############################
+set neg_mask,		0x08000000		# negative bit mask (lw)
+set inf_mask,		0x02000000		# infinity bit mask (lw)
+set z_mask,		0x04000000		# zero bit mask (lw)
+set nan_mask,		0x01000000		# nan bit mask (lw)
+
+set neg_bmask,		0x08			# negative bit mask (byte)
+set inf_bmask,		0x02			# infinity bit mask (byte)
+set z_bmask,		0x04			# zero bit mask (byte)
+set nan_bmask,		0x01			# nan bit mask (byte)
+
+set bsun_mask,		0x00008000		# bsun exception mask
+set snan_mask,		0x00004000		# snan exception mask
+set operr_mask,		0x00002000		# operr exception mask
+set ovfl_mask,		0x00001000		# overflow exception mask
+set unfl_mask,		0x00000800		# underflow exception mask
+set dz_mask,		0x00000400		# dz exception mask
+set inex2_mask,		0x00000200		# inex2 exception mask
+set inex1_mask,		0x00000100		# inex1 exception mask
+
+set aiop_mask,		0x00000080		# accrued illegal operation
+set aovfl_mask,		0x00000040		# accrued overflow
+set aunfl_mask,		0x00000020		# accrued underflow
+set adz_mask,		0x00000010		# accrued divide by zero
+set ainex_mask,		0x00000008		# accrued inexact
+
+######################################
+# FPSR combinations used in the FPSP #
+######################################
+set dzinf_mask,		inf_mask+dz_mask+adz_mask
+set opnan_mask,		nan_mask+operr_mask+aiop_mask
+set nzi_mask,		0x01ffffff		#clears N, Z, and I
+set unfinx_mask,	unfl_mask+inex2_mask+aunfl_mask+ainex_mask
+set unf2inx_mask,	unfl_mask+inex2_mask+ainex_mask
+set ovfinx_mask,	ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
+set inx1a_mask,		inex1_mask+ainex_mask
+set inx2a_mask,		inex2_mask+ainex_mask
+set snaniop_mask,	nan_mask+snan_mask+aiop_mask
+set snaniop2_mask,	snan_mask+aiop_mask
+set naniop_mask,	nan_mask+aiop_mask
+set neginf_mask,	neg_mask+inf_mask
+set infaiop_mask,	inf_mask+aiop_mask
+set negz_mask,		neg_mask+z_mask
+set opaop_mask,		operr_mask+aiop_mask
+set unfl_inx_mask,	unfl_mask+aunfl_mask+ainex_mask
+set ovfl_inx_mask,	ovfl_mask+aovfl_mask+ainex_mask
+
+#########
+# misc. #
+#########
+set rnd_stky_bit,	29			# stky bit pos in longword
+
+set sign_bit,		0x7			# sign bit
+set signan_bit,		0x6			# signalling nan bit
+
+set sgl_thresh,		0x3f81			# minimum sgl exponent
+set dbl_thresh,		0x3c01			# minimum dbl exponent
+
+set x_mode,		0x0			# extended precision
+set s_mode,		0x4			# single precision
+set d_mode,		0x8			# double precision
+
+set rn_mode,		0x0			# round-to-nearest
+set rz_mode,		0x1			# round-to-zero
+set rm_mode,		0x2			# round-tp-minus-infinity
+set rp_mode,		0x3			# round-to-plus-infinity
+
+set mantissalen,	64			# length of mantissa in bits
+
+set BYTE,		1			# len(byte) == 1 byte
+set WORD,		2			# len(word) == 2 bytes
+set LONG,		4			# len(longword) == 2 bytes
+
+set BSUN_VEC,		0xc0			# bsun    vector offset
+set INEX_VEC,		0xc4			# inexact vector offset
+set DZ_VEC,		0xc8			# dz      vector offset
+set UNFL_VEC,		0xcc			# unfl    vector offset
+set OPERR_VEC,		0xd0			# operr   vector offset
+set OVFL_VEC,		0xd4			# ovfl    vector offset
+set SNAN_VEC,		0xd8			# snan    vector offset
+
+###########################
+# SPecial CONDition FLaGs #
+###########################
+set ftrapcc_flg,	0x01			# flag bit: ftrapcc exception
+set fbsun_flg,		0x02			# flag bit: bsun exception
+set mia7_flg,		0x04			# flag bit: (a7)+ <ea>
+set mda7_flg,		0x08			# flag bit: -(a7) <ea>
+set fmovm_flg,		0x40			# flag bit: fmovm instruction
+set immed_flg,		0x80			# flag bit: &<data> <ea>
+
+set ftrapcc_bit,	0x0
+set fbsun_bit,		0x1
+set mia7_bit,		0x2
+set mda7_bit,		0x3
+set immed_bit,		0x7
+
+##################################
+# TRANSCENDENTAL "LAST-OP" FLAGS #
+##################################
+set FMUL_OP,		0x0			# fmul instr performed last
+set FDIV_OP,		0x1			# fdiv performed last
+set FADD_OP,		0x2			# fadd performed last
+set FMOV_OP,		0x3			# fmov performed last
+
+#############
+# CONSTANTS #
+#############
+T1:	long		0x40C62D38,0xD3D64634	# 16381 LOG2 LEAD
+T2:	long		0x3D6F90AE,0xB1E75CC7	# 16381 LOG2 TRAIL
+
+PI:	long		0x40000000,0xC90FDAA2,0x2168C235,0x00000000
+PIBY2:	long		0x3FFF0000,0xC90FDAA2,0x2168C235,0x00000000
+
+TWOBYPI:
+	long		0x3FE45F30,0x6DC9C883
+
+#########################################################################
+# MONADIC TEMPLATE							#
+#########################################################################
+	global		_fsins_
+_fsins_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%a6)	# save d0-d1/a0-a1
+	fmovm.l		%fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
+	fmovm.x		&0xc0,EXC_FP0(%a6)	# save fp0/fp1
+
+	fmov.l		&0x0,%fpcr		# zero FPCR
+
+#
+#	copy, convert, and tag input argument
+#
+	fmov.s		0x8(%a6),%fp0		# load sgl input
+	fmov.x		%fp0,FP_SRC(%a6)
+	lea		FP_SRC(%a6),%a0
+	bsr.l		tag			# fetch operand type
+	mov.b		%d0,STAG(%a6)
+	mov.b		%d0,%d1
+
+	andi.l		&0x00ff00ff,USER_FPSR(%a6)
+
+	clr.l		%d0
+	mov.b		FPCR_MODE(%a6),%d0	# pass rnd mode,prec
+
+	tst.b		%d1
+	bne.b		_L0_2s
+	bsr.l		ssin			# operand is a NORM
+	bra.b		_L0_6s
+_L0_2s:
+	cmpi.b		%d1,&ZERO		# is operand a ZERO?
+	bne.b		_L0_3s			# no
+	bsr.l		src_zero			# yes
+	bra.b		_L0_6s
+_L0_3s:
+	cmpi.b		%d1,&INF		# is operand an INF?
+	bne.b		_L0_4s			# no
+	bsr.l		t_operr			# yes
+	bra.b		_L0_6s
+_L0_4s:
+	cmpi.b		%d1,&QNAN		# is operand a QNAN?
+	bne.b		_L0_5s			# no
+	bsr.l		src_qnan			# yes
+	bra.b		_L0_6s
+_L0_5s:
+	bsr.l		ssind			# operand is a DENORM
+_L0_6s:
+
+#
+#	Result is now in FP0
+#
+	movm.l		EXC_DREGS(%a6),&0x0303	# restore d0-d1/a0-a1
+	fmovm.l		USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs
+	fmovm.x		EXC_FP1(%a6),&0x40	# restore fp1
+	unlk		%a6
+	rts
+
+	global		_fsind_
+_fsind_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%a6)	# save d0-d1/a0-a1
+	fmovm.l		%fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
+	fmovm.x		&0xc0,EXC_FP0(%a6)	# save fp0/fp1
+
+	fmov.l		&0x0,%fpcr		# zero FPCR
+
+#
+#	copy, convert, and tag input argument
+#
+	fmov.d		0x8(%a6),%fp0		# load dbl input
+	fmov.x		%fp0,FP_SRC(%a6)
+	lea		FP_SRC(%a6),%a0
+	bsr.l		tag			# fetch operand type
+	mov.b		%d0,STAG(%a6)
+	mov.b		%d0,%d1
+
+	andi.l		&0x00ff00ff,USER_FPSR(%a6)
+
+	clr.l		%d0
+	mov.b		FPCR_MODE(%a6),%d0	# pass rnd mode,prec
+
+	mov.b		%d1,STAG(%a6)
+	tst.b		%d1
+	bne.b		_L0_2d
+	bsr.l		ssin			# operand is a NORM
+	bra.b		_L0_6d
+_L0_2d:
+	cmpi.b		%d1,&ZERO		# is operand a ZERO?
+	bne.b		_L0_3d			# no
+	bsr.l		src_zero			# yes
+	bra.b		_L0_6d
+_L0_3d:
+	cmpi.b		%d1,&INF		# is operand an INF?
+	bne.b		_L0_4d			# no
+	bsr.l		t_operr			# yes
+	bra.b		_L0_6d
+_L0_4d:
+	cmpi.b		%d1,&QNAN		# is operand a QNAN?
+	bne.b		_L0_5d			# no
+	bsr.l		src_qnan			# yes
+	bra.b		_L0_6d
+_L0_5d:
+	bsr.l		ssind			# operand is a DENORM
+_L0_6d:
+
+#
+#	Result is now in FP0
+#
+	movm.l		EXC_DREGS(%a6),&0x0303	# restore d0-d1/a0-a1
+	fmovm.l		USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs
+	fmovm.x		EXC_FP1(%a6),&0x40	# restore fp1
+	unlk		%a6
+	rts
+
+	global		_fsinx_
+_fsinx_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%a6)	# save d0-d1/a0-a1
+	fmovm.l		%fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
+	fmovm.x		&0xc0,EXC_FP0(%a6)	# save fp0/fp1
+
+	fmov.l		&0x0,%fpcr		# zero FPCR
+
+#
+#	copy, convert, and tag input argument
+#
+	lea		FP_SRC(%a6),%a0
+	mov.l		0x8+0x0(%a6),0x0(%a0)	# load ext input
+	mov.l		0x8+0x4(%a6),0x4(%a0)
+	mov.l		0x8+0x8(%a6),0x8(%a0)
+	bsr.l		tag			# fetch operand type
+	mov.b		%d0,STAG(%a6)
+	mov.b		%d0,%d1
+
+	andi.l		&0x00ff00ff,USER_FPSR(%a6)
+
+	clr.l		%d0
+	mov.b		FPCR_MODE(%a6),%d0	# pass rnd mode,prec
+
+	tst.b		%d1
+	bne.b		_L0_2x
+	bsr.l		ssin			# operand is a NORM
+	bra.b		_L0_6x
+_L0_2x:
+	cmpi.b		%d1,&ZERO		# is operand a ZERO?
+	bne.b		_L0_3x			# no
+	bsr.l		src_zero			# yes
+	bra.b		_L0_6x
+_L0_3x:
+	cmpi.b		%d1,&INF		# is operand an INF?
+	bne.b		_L0_4x			# no
+	bsr.l		t_operr			# yes
+	bra.b		_L0_6x
+_L0_4x:
+	cmpi.b		%d1,&QNAN		# is operand a QNAN?
+	bne.b		_L0_5x			# no
+	bsr.l		src_qnan			# yes
+	bra.b		_L0_6x
+_L0_5x:
+	bsr.l		ssind			# operand is a DENORM
+_L0_6x:
+
+#
+#	Result is now in FP0
+#
+	movm.l		EXC_DREGS(%a6),&0x0303	# restore d0-d1/a0-a1
+	fmovm.l		USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs
+	fmovm.x		EXC_FP1(%a6),&0x40	# restore fp1
+	unlk		%a6
+	rts
+
+
+#########################################################################
+# MONADIC TEMPLATE							#
+#########################################################################
+	global		_fcoss_
+_fcoss_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%a6)	# save d0-d1/a0-a1
+	fmovm.l		%fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
+	fmovm.x		&0xc0,EXC_FP0(%a6)	# save fp0/fp1
+
+	fmov.l		&0x0,%fpcr		# zero FPCR
+
+#
+#	copy, convert, and tag input argument
+#
+	fmov.s		0x8(%a6),%fp0		# load sgl input
+	fmov.x		%fp0,FP_SRC(%a6)
+	lea		FP_SRC(%a6),%a0
+	bsr.l		tag			# fetch operand type
+	mov.b		%d0,STAG(%a6)
+	mov.b		%d0,%d1
+
+	andi.l		&0x00ff00ff,USER_FPSR(%a6)
+
+	clr.l		%d0
+	mov.b		FPCR_MODE(%a6),%d0	# pass rnd mode,prec
+
+	tst.b		%d1
+	bne.b		_L1_2s
+	bsr.l		scos			# operand is a NORM
+	bra.b		_L1_6s
+_L1_2s:
+	cmpi.b		%d1,&ZERO		# is operand a ZERO?
+	bne.b		_L1_3s			# no
+	bsr.l		ld_pone			# yes
+	bra.b		_L1_6s
+_L1_3s:
+	cmpi.b		%d1,&INF		# is operand an INF?
+	bne.b		_L1_4s			# no
+	bsr.l		t_operr			# yes
+	bra.b		_L1_6s
+_L1_4s:
+	cmpi.b		%d1,&QNAN		# is operand a QNAN?
+	bne.b		_L1_5s			# no
+	bsr.l		src_qnan			# yes
+	bra.b		_L1_6s
+_L1_5s:
+	bsr.l		scosd			# operand is a DENORM
+_L1_6s:
+
+#
+#	Result is now in FP0
+#
+	movm.l		EXC_DREGS(%a6),&0x0303	# restore d0-d1/a0-a1
+	fmovm.l		USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs
+	fmovm.x		EXC_FP1(%a6),&0x40	# restore fp1
+	unlk		%a6
+	rts
+
+	global		_fcosd_
+_fcosd_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%a6)	# save d0-d1/a0-a1
+	fmovm.l		%fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
+	fmovm.x		&0xc0,EXC_FP0(%a6)	# save fp0/fp1
+
+	fmov.l		&0x0,%fpcr		# zero FPCR
+
+#
+#	copy, convert, and tag input argument
+#
+	fmov.d		0x8(%a6),%fp0		# load dbl input
+	fmov.x		%fp0,FP_SRC(%a6)
+	lea		FP_SRC(%a6),%a0
+	bsr.l		tag			# fetch operand type
+	mov.b		%d0,STAG(%a6)
+	mov.b		%d0,%d1
+
+	andi.l		&0x00ff00ff,USER_FPSR(%a6)
+
+	clr.l		%d0
+	mov.b		FPCR_MODE(%a6),%d0	# pass rnd mode,prec
+
+	mov.b		%d1,STAG(%a6)
+	tst.b		%d1
+	bne.b		_L1_2d
+	bsr.l		scos			# operand is a NORM
+	bra.b		_L1_6d
+_L1_2d:
+	cmpi.b		%d1,&ZERO		# is operand a ZERO?
+	bne.b		_L1_3d			# no
+	bsr.l		ld_pone			# yes
+	bra.b		_L1_6d
+_L1_3d:
+	cmpi.b		%d1,&INF		# is operand an INF?
+	bne.b		_L1_4d			# no
+	bsr.l		t_operr			# yes
+	bra.b		_L1_6d
+_L1_4d:
+	cmpi.b		%d1,&QNAN		# is operand a QNAN?
+	bne.b		_L1_5d			# no
+	bsr.l		src_qnan			# yes
+	bra.b		_L1_6d
+_L1_5d:
+	bsr.l		scosd			# operand is a DENORM
+_L1_6d:
+
+#
+#	Result is now in FP0
+#
+	movm.l		EXC_DREGS(%a6),&0x0303	# restore d0-d1/a0-a1
+	fmovm.l		USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs
+	fmovm.x		EXC_FP1(%a6),&0x40	# restore fp1
+	unlk		%a6
+	rts
+
+	global		_fcosx_
+_fcosx_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%a6)	# save d0-d1/a0-a1
+	fmovm.l		%fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
+	fmovm.x		&0xc0,EXC_FP0(%a6)	# save fp0/fp1
+
+	fmov.l		&0x0,%fpcr		# zero FPCR
+
+#
+#	copy, convert, and tag input argument
+#
+	lea		FP_SRC(%a6),%a0
+	mov.l		0x8+0x0(%a6),0x0(%a0)	# load ext input
+	mov.l		0x8+0x4(%a6),0x4(%a0)
+	mov.l		0x8+0x8(%a6),0x8(%a0)
+	bsr.l		tag			# fetch operand type
+	mov.b		%d0,STAG(%a6)
+	mov.b		%d0,%d1
+
+	andi.l		&0x00ff00ff,USER_FPSR(%a6)
+
+	clr.l		%d0
+	mov.b		FPCR_MODE(%a6),%d0	# pass rnd mode,prec
+
+	tst.b		%d1
+	bne.b		_L1_2x
+	bsr.l		scos			# operand is a NORM
+	bra.b		_L1_6x
+_L1_2x:
+	cmpi.b		%d1,&ZERO		# is operand a ZERO?
+	bne.b		_L1_3x			# no
+	bsr.l		ld_pone			# yes
+	bra.b		_L1_6x
+_L1_3x:
+	cmpi.b		%d1,&INF		# is operand an INF?
+	bne.b		_L1_4x			# no
+	bsr.l		t_operr			# yes
+	bra.b		_L1_6x
+_L1_4x:
+	cmpi.b		%d1,&QNAN		# is operand a QNAN?
+	bne.b		_L1_5x			# no
+	bsr.l		src_qnan			# yes
+	bra.b		_L1_6x
+_L1_5x:
+	bsr.l		scosd			# operand is a DENORM
+_L1_6x:
+
+#
+#	Result is now in FP0
+#
+	movm.l		EXC_DREGS(%a6),&0x0303	# restore d0-d1/a0-a1
+	fmovm.l		USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs
+	fmovm.x		EXC_FP1(%a6),&0x40	# restore fp1
+	unlk		%a6
+	rts
+
+
+#########################################################################
+# MONADIC TEMPLATE							#
+#########################################################################
+	global		_fsinhs_
+_fsinhs_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%a6)	# save d0-d1/a0-a1
+	fmovm.l		%fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
+	fmovm.x		&0xc0,EXC_FP0(%a6)	# save fp0/fp1
+
+	fmov.l		&0x0,%fpcr		# zero FPCR
+
+#
+#	copy, convert, and tag input argument
+#
+	fmov.s		0x8(%a6),%fp0		# load sgl input
+	fmov.x		%fp0,FP_SRC(%a6)
+	lea		FP_SRC(%a6),%a0
+	bsr.l		tag			# fetch operand type
+	mov.b		%d0,STAG(%a6)
+	mov.b		%d0,%d1
+
+	andi.l		&0x00ff00ff,USER_FPSR(%a6)
+
+	clr.l		%d0
+	mov.b		FPCR_MODE(%a6),%d0	# pass rnd mode,prec
+
+	tst.b		%d1
+	bne.b		_L2_2s
+	bsr.l		ssinh			# operand is a NORM
+	bra.b		_L2_6s
+_L2_2s:
+	cmpi.b		%d1,&ZERO		# is operand a ZERO?
+	bne.b		_L2_3s			# no
+	bsr.l		src_zero			# yes
+	bra.b		_L2_6s
+_L2_3s:
+	cmpi.b		%d1,&INF		# is operand an INF?
+	bne.b		_L2_4s			# no
+	bsr.l		src_inf			# yes
+	bra.b		_L2_6s
+_L2_4s:
+	cmpi.b		%d1,&QNAN		# is operand a QNAN?
+	bne.b		_L2_5s			# no
+	bsr.l		src_qnan			# yes
+	bra.b		_L2_6s
+_L2_5s:
+	bsr.l		ssinhd			# operand is a DENORM
+_L2_6s:
+
+#
+#	Result is now in FP0
+#
+	movm.l		EXC_DREGS(%a6),&0x0303	# restore d0-d1/a0-a1
+	fmovm.l		USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs
+	fmovm.x		EXC_FP1(%a6),&0x40	# restore fp1
+	unlk		%a6
+	rts
+
+	global		_fsinhd_
+_fsinhd_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%a6)	# save d0-d1/a0-a1
+	fmovm.l		%fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
+	fmovm.x		&0xc0,EXC_FP0(%a6)	# save fp0/fp1
+
+	fmov.l		&0x0,%fpcr		# zero FPCR
+
+#
+#	copy, convert, and tag input argument
+#
+	fmov.d		0x8(%a6),%fp0		# load dbl input
+	fmov.x		%fp0,FP_SRC(%a6)
+	lea		FP_SRC(%a6),%a0
+	bsr.l		tag			# fetch operand type
+	mov.b		%d0,STAG(%a6)
+	mov.b		%d0,%d1
+
+	andi.l		&0x00ff00ff,USER_FPSR(%a6)
+
+	clr.l		%d0
+	mov.b		FPCR_MODE(%a6),%d0	# pass rnd mode,prec
+
+	mov.b		%d1,STAG(%a6)
+	tst.b		%d1
+	bne.b		_L2_2d
+	bsr.l		ssinh			# operand is a NORM
+	bra.b		_L2_6d
+_L2_2d:
+	cmpi.b		%d1,&ZERO		# is operand a ZERO?
+	bne.b		_L2_3d			# no
+	bsr.l		src_zero			# yes
+	bra.b		_L2_6d
+_L2_3d:
+	cmpi.b		%d1,&INF		# is operand an INF?
+	bne.b		_L2_4d			# no
+	bsr.l		src_inf			# yes
+	bra.b		_L2_6d
+_L2_4d:
+	cmpi.b		%d1,&QNAN		# is operand a QNAN?
+	bne.b		_L2_5d			# no
+	bsr.l		src_qnan			# yes
+	bra.b		_L2_6d
+_L2_5d:
+	bsr.l		ssinhd			# operand is a DENORM
+_L2_6d:
+
+#
+#	Result is now in FP0
+#
+	movm.l		EXC_DREGS(%a6),&0x0303	# restore d0-d1/a0-a1
+	fmovm.l		USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs
+	fmovm.x		EXC_FP1(%a6),&0x40	# restore fp1
+	unlk		%a6
+	rts
+
+	global		_fsinhx_
+_fsinhx_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%a6)	# save d0-d1/a0-a1
+	fmovm.l		%fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
+	fmovm.x		&0xc0,EXC_FP0(%a6)	# save fp0/fp1
+
+	fmov.l		&0x0,%fpcr		# zero FPCR
+
+#
+#	copy, convert, and tag input argument
+#
+	lea		FP_SRC(%a6),%a0
+	mov.l		0x8+0x0(%a6),0x0(%a0)	# load ext input
+	mov.l		0x8+0x4(%a6),0x4(%a0)
+	mov.l		0x8+0x8(%a6),0x8(%a0)
+	bsr.l		tag			# fetch operand type
+	mov.b		%d0,STAG(%a6)
+	mov.b		%d0,%d1
+
+	andi.l		&0x00ff00ff,USER_FPSR(%a6)
+
+	clr.l		%d0
+	mov.b		FPCR_MODE(%a6),%d0	# pass rnd mode,prec
+
+	tst.b		%d1
+	bne.b		_L2_2x
+	bsr.l		ssinh			# operand is a NORM
+	bra.b		_L2_6x
+_L2_2x:
+	cmpi.b		%d1,&ZERO		# is operand a ZERO?
+	bne.b		_L2_3x			# no
+	bsr.l		src_zero			# yes
+	bra.b		_L2_6x
+_L2_3x:
+	cmpi.b		%d1,&INF		# is operand an INF?
+	bne.b		_L2_4x			# no
+	bsr.l		src_inf			# yes
+	bra.b		_L2_6x
+_L2_4x:
+	cmpi.b		%d1,&QNAN		# is operand a QNAN?
+	bne.b		_L2_5x			# no
+	bsr.l		src_qnan			# yes
+	bra.b		_L2_6x
+_L2_5x:
+	bsr.l		ssinhd			# operand is a DENORM
+_L2_6x:
+
+#
+#	Result is now in FP0
+#
+	movm.l		EXC_DREGS(%a6),&0x0303	# restore d0-d1/a0-a1
+	fmovm.l		USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs
+	fmovm.x		EXC_FP1(%a6),&0x40	# restore fp1
+	unlk		%a6
+	rts
+
+
+#########################################################################
+# MONADIC TEMPLATE							#
+#########################################################################
+	global		_flognp1s_
+_flognp1s_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%a6)	# save d0-d1/a0-a1
+	fmovm.l		%fpcr,%fpsr,USER_FPCR(%a6) # save ctrl regs
+	fmovm.x		&0xc0,EXC_FP0(%a6)	# save fp0/fp1
+
+	fmov.l		&0x0,%fpcr		# zero FPCR
+
+#
+#	copy, convert, and tag input argument
+#
+	fmov.s		0x8(%a6),%fp0		# load sgl input
+	fmov.x		%fp0,FP_SRC(%a6)
+	lea		FP_SRC(%a6),%a0
+	bsr.l		tag			# fetch operand type
+	mov.b		%d0,STAG(%a6)
+	mov.b		%d0,%d1
+
+	andi.l		&0x00ff00ff,USER_FPSR(%a6)
+
+	clr.l		%d0
+	mov.b		FPCR_MODE(%a6),%d0	# pass rnd mode,prec
+
+	tst.b		%d1
+	bne.b		_L3_2s
+	bsr.l		slognp1			# operand is a NORM
+	bra.b		_L3_6s
+_L3_2s:
+	cmpi.b		%d1,&ZERO		# is operand a ZERO?
+	bne.b		_L3_3s			# no
+	bsr.l		src_zero			# yes
+	bra.b		_L3_6s
+_L3_3s:
+	cmpi.b		%d1,&INF		# is operand an INF?
+	bne.b		_L3_4s			# no
+	bsr.l		sopr_inf			# yes
+	bra.b		_L3_6s
+_L3_4s:
+	cmpi.b		%d1,&QNAN		# is operand a QNAN?
+	bne.b		_L3_5s			# no
+	bsr.l		src_qnan			# yes
+	bra.b		_L3_6s
+_L3_5s:
+	bsr.l		slognp1d			# operand is a DENORM
+_L3_6s:
+
+#
+#	Result is now in FP0
+#
+	movm.l		EXC_DREGS(%a6),&0x0303	# restore d0-d1/a0-a1
+	fmovm.l		USER_FPCR(%a6),%fpcr,%fpsr # restore ctrl regs
+	fmovm.x		EXC_FP1(%a6),&0x40	# restore fp1
+	unlk		%a6
+	rts
+
+	global		_flognp1d_
+_flognp1d_:
+	link		%a6,&-LOCAL_SIZE
+
+	movm.l		&0x0303,EXC_DREGS(%