diff options
| author | Rafael J. Wysocki <rjw@sisk.pl> | 2009-12-06 16:06:11 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rjw@sisk.pl> | 2009-12-06 16:06:11 +0100 |
| commit | 64357ed468025614d48daa6cc87674ae5616f8fb (patch) | |
| tree | 2467c239364d7602755b73203025d329c6f84b22 /arch/blackfin/mach-bf561 | |
| parent | be404f0212ffa8f67361f8ee460a25d901d88991 (diff) | |
| parent | 6ec22f9b037fc0c2e00ddb7023fad279c365324d (diff) | |
Merge branch 'master' into for-linus
Diffstat (limited to 'arch/blackfin/mach-bf561')
| -rw-r--r-- | arch/blackfin/mach-bf561/atomic.S | 14 | ||||
| -rw-r--r-- | arch/blackfin/mach-bf561/include/mach/anomaly.h | 25 |
2 files changed, 32 insertions, 7 deletions
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S index 0261a5e751b..f99f174b129 100644 --- a/arch/blackfin/mach-bf561/atomic.S +++ b/arch/blackfin/mach-bf561/atomic.S @@ -19,6 +19,16 @@ \reg\().h = _corelock; .endm +.macro safe_testset addr:req, scratch:req +#if ANOMALY_05000477 + cli \scratch; + testset (\addr); + sti \scratch; +#else + testset (\addr); +#endif +.endm + /* * r0 = address of atomic data to flush and invalidate (32bit). * @@ -33,7 +43,7 @@ ENTRY(_get_core_lock) cli r0; coreslot_loadaddr p0; .Lretry_corelock: - testset (p0); + safe_testset p0, r2; if cc jump .Ldone_corelock; SSYNC(r2); jump .Lretry_corelock @@ -56,7 +66,7 @@ ENTRY(_get_core_lock_noflush) cli r0; coreslot_loadaddr p0; .Lretry_corelock_noflush: - testset (p0); + safe_testset p0, r2; if cc jump .Ldone_corelock_noflush; SSYNC(r2); jump .Lretry_corelock_noflush diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index 70da495c966..5ddc981e993 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h @@ -1,9 +1,13 @@ /* - * File: include/asm-blackfin/mach-bf561/anomaly.h - * Bugs: Enter bugs at http://blackfin.uclinux.org/ + * DO NOT EDIT THIS FILE + * This file is under version control at + * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ + * and can be replaced with that version at any time + * DO NOT EDIT THIS FILE * - * Copyright (C) 2004-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. + * Copyright 2004-2009 Analog Devices Inc. + * Licensed under the ADI BSD license. + * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd */ /* This file should be up to date with: @@ -213,7 +217,11 @@ /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ #define ANOMALY_05000278 (__SILICON_REVISION__ < 5) /* False Hardware Error Exception when ISR Context Is Not Restored */ -#define ANOMALY_05000281 (__SILICON_REVISION__ < 5) +/* Temporarily walk around for bug 5423 till this issue is confirmed by + * official anomaly document. It looks 05000281 still exists on bf561 + * v0.5. + */ +#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5) /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */ #define ANOMALY_05000283 (1) /* Reads Will Receive Incorrect Data under Certain Conditions */ @@ -280,6 +288,12 @@ #define ANOMALY_05000443 (1) /* False Hardware Error when RETI Points to Invalid Memory */ #define ANOMALY_05000461 (1) +/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */ +#define ANOMALY_05000473 (1) +/* Core Hang With L2/L3 Configured in Writeback Cache Mode */ +#define ANOMALY_05000475 (__SILICON_REVISION__ < 4) +/* TESTSET Instruction Cannot Be Interrupted */ +#define ANOMALY_05000477 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000119 (0) @@ -304,5 +318,6 @@ #define ANOMALY_05000450 (0) #define ANOMALY_05000465 (0) #define ANOMALY_05000467 (0) +#define ANOMALY_05000474 (0) #endif |