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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-09-12 12:02:26 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-09-12 12:02:26 +0100
commitddd559b13f6d2fe3ad68c4b3f5235fd3c2eae4e3 (patch)
treed827bca3fc825a0ac33efbcd493713be40fcc812 /arch/blackfin/mach-bf561/include/mach/mem_map.h
parentcf7a2b4fb6a9b86779930a0a123b0df41aa9208f (diff)
parentf17a1f06d2fa93f4825be572622eb02c4894db4e (diff)
Merge branch 'devel-stable' into devel
Conflicts: MAINTAINERS arch/arm/mm/fault.c
Diffstat (limited to 'arch/blackfin/mach-bf561/include/mach/mem_map.h')
-rw-r--r--arch/blackfin/mach-bf561/include/mach/mem_map.h23
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index a63e15c86d9..5b96ea549a0 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -37,7 +37,6 @@
/* Memory Map for ADSP-BF561 processors */
-#ifdef CONFIG_BF561
#define COREA_L1_CODE_START 0xFFA00000
#define COREA_L1_DATA_A_START 0xFF800000
#define COREA_L1_DATA_B_START 0xFF900000
@@ -74,6 +73,28 @@
#define BFIN_DCACHESIZE (0*1024)
#define BFIN_DSUPBANKS 0
#endif /*CONFIG_BFIN_DCACHE*/
+
+/*
+ * If we are in SMP mode, then the cache settings of Core B will match
+ * the settings of Core A. If we aren't, then we assume Core B is not
+ * using any cache. This allows the rest of the kernel to work with
+ * the core in either mode as we are only loading user code into it and
+ * it is the user's problem to make sure they aren't doing something
+ * stupid there.
+ *
+ * Note that we treat the L1 code region as a contiguous blob to make
+ * the rest of the kernel simpler. Easier to check one region than a
+ * bunch of small ones. Again, possible misbehavior here is the fault
+ * of the user -- don't try to use memory that doesn't exist.
+ */
+#ifdef CONFIG_SMP
+# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH
+# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
+# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
+#else
+# define COREB_L1_CODE_LENGTH 0x14000
+# define COREB_L1_DATA_A_LENGTH 0x8000
+# define COREB_L1_DATA_B_LENGTH 0x8000
#endif
/* Level 2 Memory */