diff options
| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-10-07 19:08:56 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-07 19:08:56 +0100 |
| commit | 5a89770daad83df74d77a8d34a1ffaedae565ce9 (patch) | |
| tree | 0d8ef70293a6ef969ba8b7718e59608337643d40 /arch/blackfin/include/asm/cache.h | |
| parent | c46c948260f41af18b277c1eb1895d788d3605dc (diff) | |
| parent | af7c951d76708c61b862463d579d76be757130bf (diff) | |
Merge branches 'pxa-core' and 'pxa-machines' into pxa-all
Conflicts:
arch/arm/mach-pxa/Kconfig
arch/arm/mach-pxa/pxa25x.c
arch/arm/mach-pxa/pxa27x.c
Diffstat (limited to 'arch/blackfin/include/asm/cache.h')
| -rw-r--r-- | arch/blackfin/include/asm/cache.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h new file mode 100644 index 00000000000..023d72133b5 --- /dev/null +++ b/arch/blackfin/include/asm/cache.h @@ -0,0 +1,29 @@ +/* + * include/asm-blackfin/cache.h + */ +#ifndef __ARCH_BLACKFIN_CACHE_H +#define __ARCH_BLACKFIN_CACHE_H + +/* + * Bytes per L1 cache line + * Blackfin loads 32 bytes for cache + */ +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +/* + * Put cacheline_aliged data to L1 data memory + */ +#ifdef CONFIG_CACHELINE_ALIGNED_L1 +#define __cacheline_aligned \ + __attribute__((__aligned__(L1_CACHE_BYTES), \ + __section__(".data_l1.cacheline_aligned"))) +#endif + +/* + * largest L1 which this arch supports + */ +#define L1_CACHE_SHIFT_MAX 5 + +#endif |