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authorHans-Christian Egtvedt <hcegtvedt@atmel.com>2007-12-19 09:29:19 +0100
committerHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2008-04-19 20:40:08 -0400
commit35bf50ccc80584a1404982f02fc4368e991ff55c (patch)
treebb9add62acc4151b36c88b6bc893dc2000f08029 /arch/avr32/configs/atngw100_defconfig
parente723ff666a5da8f7fda4e36ebfeafac2175a5c6e (diff)
avr32: Implement set_rate(), set_parent() and mode() for pll1
This patch is a take two of adding full functionality to PLL1 on AT32AP7000. This allows board-specific code and drivers to configure and enable PLL1. This is useful when precise control over the frequency of e.g. a genclock is needed and requested by users for the ABDAC device. The patch is based upon previous patches from both Haavard Skinnemoen and David Brownell. Signed-off-by: Hans-Christian Egtvedt <hcegtvedt@atmel.com> Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Diffstat (limited to 'arch/avr32/configs/atngw100_defconfig')
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