diff options
| author | Alex Raimondi <mailinglist@miromico.ch> | 2008-12-09 16:17:13 +0100 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2009-01-05 15:52:04 +0100 |
| commit | dd5e1339e528197abdb7827663ff0673797fa088 (patch) | |
| tree | 0cd6eeffbd2c817020a9ef1f1795a31f5c7328d9 /arch/avr32/Kconfig | |
| parent | bc08969fe638bb164915aadd1dc1a21194847000 (diff) | |
avr32: Hammerhead board support
The Hammerhead platform is built around a AVR32 32-bit microcontroller
from Atmel. It offers versatile peripherals, such as ethernet, usb
device, usb host etc.
The board also incooperates a power supply and is a Power over Ethernet
(PoE) Powered Device (PD).
Additonally, a Cyclone III FPGA from Altera is integrated on the board.
The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two
DDR2 SDRAM interfaces, which will cover even the most exceptional need
of memory bandwidth. Together with the onboard video decoder the board
is ready for video processing.
This patch does include the basic support for the fpga device driver,
but not the device driver itself.
Signed-off-by: Alex Raimondi <mailinglist@miromico.ch>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Diffstat (limited to 'arch/avr32/Kconfig')
| -rw-r--r-- | arch/avr32/Kconfig | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index 26eca87f673..b189680d18b 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig @@ -122,6 +122,24 @@ config BOARD_ATNGW100 bool "ATNGW100 Network Gateway" select CPU_AT32AP7000 +config BOARD_HAMMERHEAD + bool "Hammerhead board" + select CPU_AT32AP7000 + select USB_ARCH_HAS_HCD + help + The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. + It offers versatile peripherals, such as ethernet, usb device, usb host etc. + + The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered + Device (PD). + + Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is + mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which + will cover even the most exceptional need of memory bandwidth. Together with the onboard + video decoder the board is ready for video processing. + + For more information see: http://www.miromico.com/hammerhead + config BOARD_FAVR_32 bool "Favr-32 LCD-board" select CPU_AT32AP7000 @@ -133,6 +151,7 @@ endchoice source "arch/avr32/boards/atstk1000/Kconfig" source "arch/avr32/boards/atngw100/Kconfig" +source "arch/avr32/boards/hammerhead/Kconfig" source "arch/avr32/boards/favr-32/Kconfig" choice |