diff options
| author | Stephen Warren <swarren@nvidia.com> | 2012-04-12 14:09:39 -0600 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-04-25 15:22:09 -0600 |
| commit | 60f975b98cf41476ba0e156f7523b197b046cf2b (patch) | |
| tree | 1af645f32f8aa377307e18876b4296586c18df95 /arch/arm | |
| parent | c8b62ab41f76218efca5e4baa5c22ef52a9fe3a5 (diff) | |
ARM: tegra: reparent sclk to pll_c_out1
pll_p_out4 needs to be used for other purposes. Reparent sclk so that
it runs from pll_c. Change sclk's rate to 120MHz from 108MHz since this
is the lowest precise rate that can be achieved by dividing the pll_c
rate without reducing the sclk rate. (600/5=120, 600/5.5=109.0909...,
600/6=100).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 22df10fb997..e9690041868 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -83,8 +83,10 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { { "pll_p_out2", "pll_p", 48000000, true }, { "pll_p_out3", "pll_p", 72000000, true }, { "pll_p_out4", "pll_p", 108000000, true }, - { "sclk", "pll_p_out4", 108000000, true }, - { "hclk", "sclk", 108000000, true }, + { "pll_c", "clk_m", 600000000, true }, + { "pll_c_out1", "pll_c", 120000000, true }, + { "sclk", "pll_c_out1", 120000000, true }, + { "hclk", "sclk", 120000000, true }, { "pclk", "hclk", 54000000, true }, { "csite", NULL, 0, true }, { "emc", NULL, 0, true }, |