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authorNicolas Pitre <nico@cam.org>2008-11-08 21:15:53 +0100
committerGreg Kroah-Hartman <gregkh@suse.de>2008-11-20 14:54:43 -0800
commit5cf84123715843d404211bc57487ecbadcd3d4c2 (patch)
treeb0041478f9d58878136cad03bb51e0a57d4b697a /arch/arm
parentc4ae2887fba8c33d67feaf00726474eda04d5dd6 (diff)
ARM: 5329/1: Feroceon: fix feroceon_l2_inv_range
commit 72bc2b1ad62f4d2f0a51b35829093d41f55accce upstream. Same fix as commit c7cf72dcadb: when 'start' and 'end' are less than a cacheline apart and 'start' is unaligned we are done after cleaning and invalidating the first cacheline. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mm/cache-feroceon-l2.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index 7b5a25d8157..4f6cf46a546 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -148,7 +148,7 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
/*
* Clean and invalidate partial last cache line.
*/
- if (end & (CACHE_LINE_SIZE - 1)) {
+ if (start < end && end & (CACHE_LINE_SIZE - 1)) {
l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
end &= ~(CACHE_LINE_SIZE - 1);
}
@@ -156,7 +156,7 @@ static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
/*
* Invalidate all full cache lines between 'start' and 'end'.
*/
- while (start != end) {
+ while (start < end) {
unsigned long range_end = calc_range_end(start, end);
l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
start = range_end;