diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-12-18 16:17:37 +0000 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2008-12-18 16:17:37 +0000 |
commit | 56c035c9ce1f1850969778af6a4cc0b99089b6c8 (patch) | |
tree | b6f1998be0c1e6bb623a0c55e8ba04d74bb58cf2 /arch/arm/plat-s3c64xx | |
parent | 7f2754378f3522a42daafdbb9d2385f341008454 (diff) | |
parent | 438a5d42e052ec6126c5f1e24763b711210db33e (diff) |
Merge branch 'next-s3c64xx-device' into next-merged
Conflicts:
arch/arm/mach-s3c2440/mach-at2440evb.c
Diffstat (limited to 'arch/arm/plat-s3c64xx')
22 files changed, 1347 insertions, 0 deletions
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index bd832ba0cf7..203dd730d1c 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -14,6 +14,10 @@ config PLAT_S3C64XX default y select NO_IOPORT select ARCH_REQUIRE_GPIOLIB + select S3C_GPIO_TRACK + select S3C_GPIO_PULL_UPDOWN + select S3C_GPIO_CFG_S3C24XX + select S3C_GPIO_CFG_S3C64XX help Base platform code for any Samsung S3C64XX device @@ -33,4 +37,25 @@ config CPU_S3C6400_CLOCK Common clock support code for the S3C6400 that is shared by other CPUs in the series, such as the S3C6410. +# platform specific device setup + +config S3C64XX_SETUP_I2C0 + bool + default y + help + Common setup code for i2c bus 0. + + Note, currently since i2c0 is always compiled, this setup helper + is always compiled with it. + +config S3C64XX_SETUP_I2C1 + bool + help + Common setup code for i2c bus 1. + +config S3C64XX_SETUP_FB_24BPP + bool + help + Common setup code for S3C64XX with an 24bpp RGB display helper. + endif diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index 9c09b081980..2e6d79bf8f3 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -17,8 +17,15 @@ obj-y += cpu.o obj-y += irq.o obj-y += irq-eint.o obj-y += clock.o +obj-y += gpiolib.o # CPU support obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o + +# Device setup + +obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o +obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o +obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c new file mode 100644 index 00000000000..cc62941d7b5 --- /dev/null +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -0,0 +1,420 @@ +/* arch/arm/plat-s3c64xx/gpiolib.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/map.h> +#include <mach/gpio.h> +#include <mach/gpio-core.h> + +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> +#include <plat/regs-gpio.h> + +/* GPIO bank summary: + * + * Bank GPIOs Style SlpCon ExtInt Group + * A 8 4Bit Yes 1 + * B 7 4Bit Yes 1 + * C 8 4Bit Yes 2 + * D 5 4Bit Yes 3 + * E 5 4Bit Yes None + * F 16 2Bit Yes 4 [1] + * G 7 4Bit Yes 5 + * H 10 4Bit[2] Yes 6 + * I 16 2Bit Yes None + * J 12 2Bit Yes None + * K 16 4Bit[2] No None + * L 15 4Bit[2] No None + * M 6 4Bit No IRQ_EINT + * N 16 2Bit No IRQ_EINT + * O 16 2Bit Yes 7 + * P 15 2Bit Yes 8 + * Q 9 2Bit Yes 9 + * + * [1] BANKF pins 14,15 do not form part of the external interrupt sources + * [2] BANK has two control registers, GPxCON0 and GPxCON1 + */ + +#define OFF_GPCON (0x00) +#define OFF_GPDAT (0x04) + +#define con_4bit_shift(__off) ((__off) * 4) + +#if 1 +#define gpio_dbg(x...) do { } while(0) +#else +#define gpio_dbg(x...) printk(KERN_DEBUG ## x) +#endif + +/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where + * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the + * following example: + * + * base + 0x00: Control register, 4 bits per gpio + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Data register, 1 bit per gpio + * bit n: data bit n + * + * Note, since the data register is one bit per gpio and is at base + 0x4 + * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of + * the output. +*/ + +static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + + con = __raw_readl(base + OFF_GPCON); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, base + OFF_GPCON); + + gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); + + return 0; +} + +static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + unsigned long dat; + + con = __raw_readl(base + OFF_GPCON); + con &= ~(0xf << con_4bit_shift(offset)); + con |= 0x1 << con_4bit_shift(offset); + + dat = __raw_readl(base + OFF_GPDAT); + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + OFF_GPDAT); + __raw_writel(con, base + OFF_GPCON); + __raw_writel(dat, base + OFF_GPDAT); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +/* The next set of routines are for the case where the GPIO configuration + * registers are 4 bits per GPIO but there is more than one register (the + * bank has more than 8 GPIOs. + * + * This case is the similar to the 4 bit case, but the registers are as + * follows: + * + * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x08: Data register, 1 bit per gpio + * bit n: data bit n + * + * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we + * store the 'base + 0x4' address so that these routines see the data + * register at ourchip->base + 0x04. +*/ + +static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + + if (offset > 7) + offset -= 8; + else + regcon -= 4; + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, regcon); + + gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); + + return 0; + +} + +static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + unsigned long dat; + + if (offset > 7) + offset -= 8; + else + regcon -= 4; + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(offset)); + con |= 0x1 << con_4bit_shift(offset); + + dat = __raw_readl(base + OFF_GPDAT); + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + OFF_GPDAT); + __raw_writel(con, regcon); + __raw_writel(dat, base + OFF_GPDAT); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = { + .cfg_eint = 7, + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { + .cfg_eint = 3, + .set_config = s3c_gpio_setcfg_s3c64xx_4bit, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_chip gpio_4bit[] = { + { + .base = S3C64XX_GPA_BASE, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPA(0), + .ngpio = S3C64XX_GPIO_A_NR, + .label = "GPA", + }, + }, { + .base = S3C64XX_GPB_BASE, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPB(0), + .ngpio = S3C64XX_GPIO_B_NR, + .label = "GPB", + }, + }, { + .base = S3C64XX_GPC_BASE, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPC(0), + .ngpio = S3C64XX_GPIO_C_NR, + .label = "GPC", + }, + }, { + .base = S3C64XX_GPD_BASE, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPD(0), + .ngpio = S3C64XX_GPIO_D_NR, + .label = "GPD", + }, + }, { + .base = S3C64XX_GPE_BASE, + .config = &gpio_4bit_cfg_noint, + .chip = { + .base = S3C64XX_GPE(0), + .ngpio = S3C64XX_GPIO_E_NR, + .label = "GPE", + }, + }, { + .base = S3C64XX_GPG_BASE, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPG(0), + .ngpio = S3C64XX_GPIO_G_NR, + .label = "GPG", + }, + }, { + .base = S3C64XX_GPM_BASE, + .config = &gpio_4bit_cfg_eint0011, + .chip = { + .base = S3C64XX_GPM(0), + .ngpio = S3C64XX_GPIO_M_NR, + .label = "GPM", + }, + }, +}; + +static struct s3c_gpio_chip gpio_4bit2[] = { + { + .base = S3C64XX_GPH_BASE + 0x4, + .config = &gpio_4bit_cfg_eint0111, + .chip = { + .base = S3C64XX_GPH(0), + .ngpio = S3C64XX_GPIO_H_NR, + .label = "GPH", + }, + }, { + .base = S3C64XX_GPK_BASE + 0x4, + .config = &gpio_4bit_cfg_noint, + .chip = { + .base = S3C64XX_GPK(0), + .ngpio = S3C64XX_GPIO_K_NR, + .label = "GPK", + }, + }, { + .base = S3C64XX_GPL_BASE + 0x4, + .config = &gpio_4bit_cfg_eint0011, + .chip = { + .base = S3C64XX_GPL(0), + .ngpio = S3C64XX_GPIO_L_NR, + .label = "GPL", + }, + }, +}; + +static struct s3c_gpio_cfg gpio_2bit_cfg_noint = { + .set_config = s3c_gpio_setcfg_s3c24xx, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = { + .cfg_eint = 2, + .set_config = s3c_gpio_setcfg_s3c24xx, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { + .cfg_eint = 3, + .set_config = s3c_gpio_setcfg_s3c24xx, + .set_pull = s3c_gpio_setpull_updown, + .get_pull = s3c_gpio_getpull_updown, +}; + +static struct s3c_gpio_chip gpio_2bit[] = { + { + .base = S3C64XX_GPF_BASE, + .config = &gpio_2bit_cfg_eint11, + .chip = { + .base = S3C64XX_GPF(0), + .ngpio = S3C64XX_GPIO_F_NR, + .label = "GPF", + }, + }, { + .base = S3C64XX_GPI_BASE, + .config = &gpio_2bit_cfg_noint, + .chip = { + .base = S3C64XX_GPI(0), + .ngpio = S3C64XX_GPIO_I_NR, + .label = "GPI", + }, + }, { + .base = S3C64XX_GPJ_BASE, + .config = &gpio_2bit_cfg_noint, + .chip = { + .base = S3C64XX_GPJ(0), + .ngpio = S3C64XX_GPIO_J_NR, + .label = "GPJ", + }, + }, { + .base = S3C64XX_GPN_BASE, + .config = &gpio_2bit_cfg_eint10, + .chip = { + .base = S3C64XX_GPN(0), + .ngpio = S3C64XX_GPIO_N_NR, + .label = "GPN", + }, + }, { + .base = S3C64XX_GPO_BASE, + .config = &gpio_2bit_cfg_eint11, + .chip = { + .base = S3C64XX_GPO(0), + .ngpio = S3C64XX_GPIO_O_NR, + .label = "GPO", + }, + }, { + .base = S3C64XX_GPP_BASE, + .config = &gpio_2bit_cfg_eint11, + .chip = { + .base = S3C64XX_GPP(0), + .ngpio = S3C64XX_GPIO_P_NR, + .label = "GPP", + }, + }, { + .base = S3C64XX_GPQ_BASE, + .config = &gpio_2bit_cfg_eint11, + .chip = { + .base = S3C64XX_GPQ(0), + .ngpio = S3C64XX_GPIO_Q_NR, + .label = "GPQ", + }, + }, +}; + +static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) +{ + chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; + chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; +} + +static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) +{ + chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; + chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; +} + +static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, + int nr_chips, + void (*fn)(struct s3c_gpio_chip *)) +{ + for (; nr_chips > 0; nr_chips--, chips++) { + if (fn) + (fn)(chips); + s3c_gpiolib_add(chips); + } +} + +static __init int s3c64xx_gpiolib_init(void) +{ + s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), + s3c64xx_gpiolib_add_4bit); + + s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), + s3c64xx_gpiolib_add_4bit2); + + s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL); + + return 0; +} + +arch_initcall(s3c64xx_gpiolib_init); diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h new file mode 100644 index 00000000000..9aa0e427d11 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h @@ -0,0 +1,48 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank A register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00) +#define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04) +#define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08) +#define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c) +#define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10) + +#define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPA0_UART_RXD0 (0x02 << 0) +#define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0) + +#define S3C64XX_GPA1_UART_TXD0 (0x02 << 4) +#define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4) + +#define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8) +#define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8) + +#define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12) +#define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12) + +#define S3C64XX_GPA4_UART_RXD1 (0x02 << 16) +#define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16) + +#define S3C64XX_GPA5_UART_TXD1 (0x02 << 20) +#define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20) + +#define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24) +#define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24) + +#define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28) +#define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h new file mode 100644 index 00000000000..3933adb4d50 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h @@ -0,0 +1,60 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank B register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00) +#define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04) +#define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08) +#define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c) +#define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10) + +#define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPB0_UART_RXD2 (0x02 << 0) +#define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0) +#define S3C64XX_GPB0_IrDA_RXD (0x04 << 0) +#define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0) +#define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0) + +#define S3C64XX_GPB1_UART_TXD2 (0x02 << 4) +#define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4) +#define S3C64XX_GPB1_IrDA_TXD (0x04 << 4) +#define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4) +#define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4) + +#define S3C64XX_GPB2_UART_RXD3 (0x02 << 8) +#define S3C64XX_GPB2_IrDA_RXD (0x03 << 8) +#define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8) +#define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8) +#define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8) +#define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8) + +#define S3C64XX_GPB3_UART_TXD3 (0x02 << 12) +#define S3C64XX_GPB3_IrDA_TXD (0x03 << 12) +#define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12) +#define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12) +#define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12) + +#define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16) +#define S3C64XX_GPB4_CAM_FIELD (0x03 << 16) +#define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16) +#define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16) + +#define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20) +#define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20) + +#define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24) +#define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h new file mode 100644 index 00000000000..c47daf7e272 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h @@ -0,0 +1,53 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank C register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00) +#define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04) +#define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08) +#define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c) +#define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10) + +#define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0) +#define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0) + +#define S3C64XX_GPC1_SPI_CLKO (0x02 << 4) +#define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4) + +#define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8) +#define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8) + +#define S3C64XX_GPC3_SPI_nCSO (0x02 << 12) +#define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12) + +#define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16) +#define S3C64XX_GPC4_MMC2_CMD (0x03 << 16) +#define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16) +#define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16) + +#define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20) +#define S3C64XX_GPC5_MMC2_CLK (0x03 << 20) +#define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20) +#define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20) + +#define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24) +#define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24) + +#define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28) +#define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28) +#define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h new file mode 100644 index 00000000000..6fe4a49c26f --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h @@ -0,0 +1,49 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank D register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00) +#define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04) +#define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08) +#define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c) +#define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10) + +#define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0) +#define S3C64XX_GPD0_I2S0_CLK (0x03 << 0) +#define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0) +#define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0) + +#define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4) +#define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4) +#define S3C64XX_GPD1_AC97_nRESET (0x04 << 4) +#define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4) + +#define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8) +#define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8) +#define S3C64XX_GPD2_AC97_SYNC (0x04 << 8) +#define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8) + +#define S3C64XX_GPD3_PCM0_SIN (0x02 << 12) +#define S3C64XX_GPD3_I2S0_DI (0x03 << 12) +#define S3C64XX_GPD3_AC97_SDI (0x04 << 12) +#define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12) + +#define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16) +#define S3C64XX_GPD4_I2S0_D0 (0x03 << 16) +#define S3C64XX_GPD4_AC97_SDO (0x04 << 16) +#define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h new file mode 100644 index 00000000000..7fcf3d8e0a4 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h @@ -0,0 +1,44 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank E register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00) +#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04) +#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08) +#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c) +#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10) + +#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0) +#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0) +#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0) + +#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4) +#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4) +#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4) + +#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8) +#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8) +#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8) + +#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12) +#define S3C64XX_GPE3_I2S1_DI (0x03 << 12) +#define S3C64XX_GPE3_AC97_SDI (0x04 << 12) + +#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16) +#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16) +#define S3C64XX_GPE4_AC97_SDO (0x04 << 16) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h new file mode 100644 index 00000000000..f3faff974a1 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h @@ -0,0 +1,71 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank F register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00) +#define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04) +#define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08) +#define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c) +#define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10) + +#define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0) +#define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0) + +#define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2) +#define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2) + +#define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4) +#define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4) + +#define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6) +#define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6) + +#define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8) +#define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8) + +#define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10) +#define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10) + +#define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12) +#define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12) + +#define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14) +#define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14) + +#define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16) +#define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16) + +#define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18) +#define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18) + +#define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20) +#define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20) + +#define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22) +#define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22) + +#define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24) +#define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24) + +#define S3C64XX_GPF13_PWM_ECLK (0x02 << 26) +#define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26) + +#define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28) +#define S3C64XX_GPF14_CLKOUT0 (0x03 << 28) + +#define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30) + diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h new file mode 100644 index 00000000000..35bbd2378e5 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h @@ -0,0 +1,42 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank G register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00) +#define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04) +#define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08) +#define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c) +#define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10) + +#define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPG0_MMC0_CLK (0x02 << 0) +#define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0) + +#define S3C64XX_GPG1_MMC0_CMD (0x02 << 4) +#define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4) + +#define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8) +#define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8) + +#define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12) +#define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12) + +#define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16) +#define S3C64XX_GPG4_EINT_G5_4 (0x07 |