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authorOlof Johansson <olof@lixom.net>2012-04-05 17:09:45 -0700
committerOlof Johansson <olof@lixom.net>2012-04-05 17:09:45 -0700
commita8f5b6e5ef0faf64997bfa87698aaabc989e64c4 (patch)
tree9eb41f6030258dc174c72c5431e690ee70ae750c /arch/arm/plat-omap
parent1ac02d795889d1828a66d4b3a3fd66492d1d7cf2 (diff)
parenta9dd31b744a033b4324c93cec4ecb4c74061e2cf (diff)
Merge tag 'omap-fixes-a2-for-3.4rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes
From Paul Walmsley: OMAP clock, powerdomain, clockdomain, and hwmod fixes intended for the early v3.4-rc series. Also contains an HSMMC integration refinement of an earlier hardware bug workaround. * tag 'omap-fixes-a2-for-3.4rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending: ARM: OMAP2+: hwmod: Fix wrong SYSC_TYPE1_XXX_MASK bit definitions ARM: OMAP2+: hwmod: Make omap_hwmod_softreset wait for reset status ARM: OMAP2+: hwmod: Restore sysc after a reset ARM: OMAP2+: omap_hwmod: Allow io_ring wakeup configuration for all modules ARM: OMAP3: clock data: fill in some missing clockdomains ARM: OMAP4: clock data: Force a DPLL clkdm/pwrdm ON before a relock ARM: OMAP4: clock data: fix mult and div mask for USB_DPLL ARM: OMAP2+: powerdomain: Wait for powerdomain transition in pwrdm_state_switch() ARM: OMAP AM3517/3505: clock data: change EMAC clocks aliases ARM: OMAP: clock: fix race in disable all clocks ARM: OMAP4: hwmod data: Add aliases for McBSP fclk clocks ARM: OMAP3xxx: clock data: fix DPLL4 CLKSEL masks ARM: OMAP3xxx: HSMMC: avoid erratum workaround when transceiver is attached ARM: OMAP44xx: clockdomain data: correct the emu_sys_clkdm CLKTRCTRL data
Diffstat (limited to 'arch/arm/plat-omap')
-rw-r--r--arch/arm/plat-omap/clock.c5
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h12
2 files changed, 9 insertions, 8 deletions
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 56b6f8b7053..8506cbb7fea 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -441,6 +441,8 @@ static int __init clk_disable_unused(void)
return 0;
pr_info("clock: disabling unused clocks to save power\n");
+
+ spin_lock_irqsave(&clockfw_lock, flags);
list_for_each_entry(ck, &clocks, node) {
if (ck->ops == &clkops_null)
continue;
@@ -448,10 +450,9 @@ static int __init clk_disable_unused(void)
if (ck->usecount > 0 || !ck->enable_reg)
continue;
- spin_lock_irqsave(&clockfw_lock, flags);
arch_clock->clk_disable_unused(ck);
- spin_unlock_irqrestore(&clockfw_lock, flags);
}
+ spin_unlock_irqrestore(&clockfw_lock, flags);
return 0;
}
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 9e8e63d52aa..8070145ccb9 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -47,17 +47,17 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
* with the original PRCM protocol defined for OMAP2420
*/
#define SYSC_TYPE1_MIDLEMODE_SHIFT 12
-#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_MIDLEMODE_SHIFT)
+#define SYSC_TYPE1_MIDLEMODE_MASK (0x3 << SYSC_TYPE1_MIDLEMODE_SHIFT)
#define SYSC_TYPE1_CLOCKACTIVITY_SHIFT 8
-#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_CLOCKACTIVITY_SHIFT)
+#define SYSC_TYPE1_CLOCKACTIVITY_MASK (0x3 << SYSC_TYPE1_CLOCKACTIVITY_SHIFT)
#define SYSC_TYPE1_SIDLEMODE_SHIFT 3
-#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_SIDLEMODE_SHIFT)
+#define SYSC_TYPE1_SIDLEMODE_MASK (0x3 << SYSC_TYPE1_SIDLEMODE_SHIFT)
#define SYSC_TYPE1_ENAWAKEUP_SHIFT 2
-#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_ENAWAKEUP_SHIFT)
+#define SYSC_TYPE1_ENAWAKEUP_MASK (1 << SYSC_TYPE1_ENAWAKEUP_SHIFT)
#define SYSC_TYPE1_SOFTRESET_SHIFT 1
-#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_SOFTRESET_SHIFT)
+#define SYSC_TYPE1_SOFTRESET_MASK (1 << SYSC_TYPE1_SOFTRESET_SHIFT)
#define SYSC_TYPE1_AUTOIDLE_SHIFT 0
-#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_AUTOIDLE_SHIFT)
+#define SYSC_TYPE1_AUTOIDLE_MASK (1 << SYSC_TYPE1_AUTOIDLE_SHIFT)
/*
* OCP SYSCONFIG bit shifts/masks TYPE2. These are for IPs compliant