aboutsummaryrefslogtreecommitdiff
path: root/arch/arm/mm/proc-sa110.S
diff options
context:
space:
mode:
authorJiri Kosina <jkosina@suse.cz>2010-08-04 15:14:38 +0200
committerJiri Kosina <jkosina@suse.cz>2010-08-04 15:14:38 +0200
commitd790d4d583aeaed9fc6f8a9f4d9f8ce6b1c15c7f (patch)
tree854ab394486288d40fa8179cbfaf66e8bdc44b0f /arch/arm/mm/proc-sa110.S
parent73b2c7165b76b20eb1290e7efebc33cfd21db1ca (diff)
parent3a09b1be53d23df780a0cd0e4087a05e2ca4a00c (diff)
Merge branch 'master' into for-next
Diffstat (limited to 'arch/arm/mm/proc-sa110.S')
-rw-r--r--arch/arm/mm/proc-sa110.S8
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 7b706b38990..a201eb04b5e 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -44,17 +44,13 @@ ENTRY(cpu_sa110_proc_init)
* cpu_sa110_proc_fin()
*/
ENTRY(cpu_sa110_proc_fin)
- stmfd sp!, {lr}
- mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
- msr cpsr_c, ip
- bl v4wb_flush_kern_cache_all @ clean caches
-1: mov r0, #0
+ mov r0, #0
mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
mrc p15, 0, r0, c1, c0, 0 @ ctrl register
bic r0, r0, #0x1000 @ ...i............
bic r0, r0, #0x000e @ ............wca.
mcr p15, 0, r0, c1, c0, 0 @ disable caches
- ldmfd sp!, {pc}
+ mov pc, lr
/*
* cpu_sa110_reset(loc)