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authorLinus Torvalds <torvalds@linux-foundation.org>2009-02-03 16:52:10 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2009-02-03 16:52:10 -0800
commit7420b73dc05ae1faa36b49774210a13d29349c53 (patch)
tree90cdba18724099353598e69b3ee9ee21df9582cf /arch/arm/mm/fault-armv.c
parent3e1c4005134e3a090c64c1bc35f965043bb451f4 (diff)
parentde8696203e64f19ea26f8e096ac8a796e78216b3 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: NVRAM depends on RTC_DRV_CMOS rename platform_driver name "flash" to "sa1100-mtd" annotate that [fp, #-4] is the saved lr Use __SPIN_LOCK_UNLOCKED to initialize bad_irq_desc.lock ARM: OMAP: fix fault in enter_full_retention() ARM: OMAP: Mask interrupts when disabling interrupts, v2 ARM: OMAP: gptimer min_delta_ns corrected ARM: OMAP: Fix hsmmc init, v2 ARM: OMAP: Fix omap34xx revision detection for ES3.1 ARM: OMAP: DMA: Fix uninitialized channel flags ARM: OMAP: Fix race in OMAP2/3 DMA IRQ handling ARM: OMAP: Fix McBSP spin_lock deadlock [ARM] 5366/1: fix shared memory coherency with VIVT L1 + L2 caches [ARM] call undefined instruction exception handler with irqs enabled [ARM] msm: fix build errors [ARM] etherh: continue fixing build failure
Diffstat (limited to 'arch/arm/mm/fault-armv.c')
-rw-r--r--arch/arm/mm/fault-armv.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 81d0b8772de..bc0099d5ae8 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -66,7 +66,10 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
* fault (ie, is old), we can safely ignore any issues.
*/
if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
- flush_cache_page(vma, address, pte_pfn(entry));
+ unsigned long pfn = pte_pfn(entry);
+ flush_cache_page(vma, address, pfn);
+ outer_flush_range((pfn << PAGE_SHIFT),
+ (pfn << PAGE_SHIFT) + PAGE_SIZE);
pte_val(entry) &= ~L_PTE_MT_MASK;
pte_val(entry) |= shared_pte_mask;
set_pte_at(vma->vm_mm, address, pte, entry);