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| author | Jiri Kosina <jkosina@suse.cz> | 2010-06-16 18:08:13 +0200 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2010-06-16 18:08:13 +0200 |
| commit | f1bbbb6912662b9f6070c5bfc4ca9eb1f06a9d5b (patch) | |
| tree | c2c130a74be25b0b2dff992e1a195e2728bdaadd /arch/arm/mm/cache-v7.S | |
| parent | fd0961ff67727482bb20ca7e8ea97b83e9de2ddb (diff) | |
| parent | 7e27d6e778cd87b6f2415515d7127eba53fe5d02 (diff) | |
Merge branch 'master' into for-next
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 06a90dcfc60..37c8157e116 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -91,7 +91,11 @@ ENTRY(v7_flush_kern_cache_all) THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) bl v7_flush_dcache_all mov r0, #0 +#ifdef CONFIG_SMP + mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable +#else mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate +#endif ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) mov pc, lr |