diff options
| author | Catalin Marinas <catalin.marinas@arm.com> | 2006-03-10 22:26:47 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-03-10 22:26:47 +0000 |
| commit | 141fa40cff90881ac4d81f6afa27bc283fe7acca (patch) | |
| tree | 7991b0f3910dafb58e1ef92044153e5383b01850 /arch/arm/mm/cache-v6.S | |
| parent | e7fcdb79ecaa01e2eba06e3fb64e10455bdb5aa7 (diff) | |
[ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem
Patch from Catalin Marinas
ARM1136 erratum 371025 (category 2) specifies that, under rare
conditions, an invalidate I-cache by MVA (line or range) operation can
fail to invalidate a cache line. The recommended workaround is to
either invalidate the entire I-cache or invalidate the range by
set/way rather than MVA.
Note that for a 16K cache size, invalidating a 4K page by set/way is
equivalent to invalidating the entire I-cache.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/cache-v6.S')
| -rw-r--r-- | arch/arm/mm/cache-v6.S | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index d921c1024ae..2c6c2a7c05a 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -96,15 +96,16 @@ ENTRY(v6_coherent_user_range) #ifdef HARVARD_CACHE bic r0, r0, #CACHE_LINE_SIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D line - mcr p15, 0, r0, c7, c5, 1 @ invalidate I line add r0, r0, #CACHE_LINE_SIZE cmp r0, r1 blo 1b #endif - mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB -#ifdef HARVARD_CACHE mov r0, #0 +#ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate +#else + mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB #endif mov pc, lr |