diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2010-02-17 18:27:37 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2010-02-17 18:28:05 +0100 |
| commit | b7e56edba4b02f2079042c326a8cd72a44635817 (patch) | |
| tree | b5042002e9747cd8fb1278d61f86d8b92a74c018 /arch/arm/mm/cache-v4wb.S | |
| parent | 13ca0fcaa33f6b1984c4111b6ec5df42689fea6f (diff) | |
| parent | b0483e78e5c4c9871fc5541875b3bc006846d46b (diff) | |
Merge branch 'linus' into x86/mm
x86/mm is on 32-rc4 and missing the spinlock namespace changes which
are needed for further commits into this topic.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/arm/mm/cache-v4wb.S')
| -rw-r--r-- | arch/arm/mm/cache-v4wb.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S index 2ebc1b3bf85..3dbedf1ec0e 100644 --- a/arch/arm/mm/cache-v4wb.S +++ b/arch/arm/mm/cache-v4wb.S @@ -114,15 +114,16 @@ ENTRY(v4wb_flush_user_cache_range) mov pc, lr /* - * flush_kern_dcache_page(void *page) + * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - page aligned address + * - addr - kernel address + * - size - region size */ -ENTRY(v4wb_flush_kern_dcache_page) - add r1, r0, #PAGE_SZ +ENTRY(v4wb_flush_kern_dcache_area) + add r1, r0, r1 /* fall through */ /* @@ -224,7 +225,7 @@ ENTRY(v4wb_cache_fns) .long v4wb_flush_user_cache_range .long v4wb_coherent_kern_range .long v4wb_coherent_user_range - .long v4wb_flush_kern_dcache_page + .long v4wb_flush_kern_dcache_area .long v4wb_dma_inv_range .long v4wb_dma_clean_range .long v4wb_dma_flush_range |