diff options
| author | Lennert Buytenhek <buytenh@marvell.com> | 2009-11-24 19:33:52 +0200 |
|---|---|---|
| committer | Nicolas Pitre <nico@fluxnic.net> | 2009-11-27 15:43:21 -0500 |
| commit | 573a652fb0da50a1ff3fca2c67afd81138fd06d2 (patch) | |
| tree | e393e667f733db56447c266d45e58accf141894f /arch/arm/mm/Kconfig | |
| parent | edabd38e1a017e922e3e3b485ee3ddb4df433aa4 (diff) | |
ARM: Add Tauros2 L2 cache controller support
Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mm/Kconfig')
| -rw-r--r-- | arch/arm/mm/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 1549863d7b5..4958ef2c625 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -764,6 +764,15 @@ config CACHE_L2X0 help This option enables the L2x0 PrimeCell. +config CACHE_TAUROS2 + bool "Enable the Tauros2 L2 cache controller" + depends on ARCH_DOVE + default y + select OUTER_CACHE + help + This option enables the Tauros2 L2 cache controller (as + found on PJ1/PJ4). + config CACHE_XSC3L2 bool "Enable the L2 cache on XScale3" depends on CPU_XSC3 |