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authorArnd Bergmann <arnd@arndb.de>2012-02-25 12:48:52 -0700
committerLinus Walleij <linus.walleij@linaro.org>2012-02-29 17:09:10 +0100
commit68526e586307faadc49c27406dad3cb93f067eb0 (patch)
tree130b84018c10f4b18c961fae087f9a8a7c7f899f /arch/arm/mach-ux500/Kconfig
parentded547a443723f0f29bce513356fe10f96cae315 (diff)
ARM: ux500: select L2X0 cache on ux500
The cache controller needs to be enabled for the cortex-a9 specific errata that are also selected to work. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/mach-ux500/Kconfig')
-rw-r--r--arch/arm/mach-ux500/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 34b631446dd..41b38bb96eb 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -8,6 +8,7 @@ config UX500_SOC_COMMON
select ARM_ERRATA_753970
select ARM_ERRATA_754322
select ARM_ERRATA_764369
+ select CACHE_L2X0
config UX500_SOC_DB5500
bool