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author | Vegard Nossum <vegard.nossum@gmail.com> | 2009-06-15 15:50:49 +0200 |
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committer | Vegard Nossum <vegard.nossum@gmail.com> | 2009-06-15 15:50:49 +0200 |
commit | 722f2a6c87f34ee0fd0130a8cf45f81e0705594a (patch) | |
tree | 50b054df34d2731eb0ba0cf1a6c27e43e7eed428 /arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h | |
parent | 7a0aeb14e18ad59394bd9bbc6e57fb345819e748 (diff) | |
parent | 45e3e1935e2857c54783291107d33323b3ef33c8 (diff) |
Merge commit 'linus/master' into HEAD
Conflicts:
MAINTAINERS
Signed-off-by: Vegard Nossum <vegard.nossum@gmail.com>
Diffstat (limited to 'arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h')
-rw-r--r-- | arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h new file mode 100644 index 00000000000..3b6d990a3af --- /dev/null +++ b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h @@ -0,0 +1,37 @@ +/* + * stmp37xx: ECC8 register definitions + * + * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000) + +#define HW_ECC8_CTRL 0x0 +#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001 +#define BP_ECC8_CTRL_COMPLETE_IRQ 0 +#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100 +#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 + +#define HW_ECC8_STATUS0 0x10 +#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004 +#define BM_ECC8_STATUS0_CORRECTED 0x00000008 +#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00 +#define BP_ECC8_STATUS0_STATUS_AUX 8 +#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000 +#define BP_ECC8_STATUS0_COMPLETED_CE 16 + +#define HW_ECC8_STATUS1 0x20 |