ARM: shmobile: r8a7740: Use driver-provided pinmux info

Pinmux info for the r8a7740 is now provided by pinmux drivers. Remove
the duplicate copy in arch code.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

3 files changed, 26 insertions, 2644 deletions

diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 0b7147928aa..fb07d8e6c15 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -23,7 +23,6 @@ smp-$(CONFIG_ARCH_EMEV2)	+= smp-emev2.o
 pfc-y				:=
 pfc-$(CONFIG_ARCH_SH7372)	+= pfc-sh7372.o
 pfc-$(CONFIG_ARCH_SH73A0)	+= pfc-sh73a0.o
-pfc-$(CONFIG_ARCH_R8A7740)	+= pfc-r8a7740.o
 pfc-$(CONFIG_ARCH_R8A7779)	+= pfc-r8a7779.o
 
 # IRQ objects
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
deleted file mode 100644
index 84ef85d8053..00000000000
--- a/arch/arm/mach-shmobile/pfc-r8a7740.c
+++ /dev/null
@@ -1,2643 +0,0 @@
-/*
- * R8A7740 processor support
- *
- * Copyright (C) 2011  Renesas Solutions Corp.
- * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the
- * License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/bug.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/sh_pfc.h>
-#include <mach/r8a7740.h>
-#include <mach/irqs.h>
-
-#define CPU_ALL_PORT(fn, pfx, sfx)					\
-	PORT_10(fn, pfx, sfx),		PORT_90(fn, pfx, sfx),		\
-	PORT_10(fn, pfx##10, sfx),	PORT_90(fn, pfx##1, sfx),	\
-	PORT_10(fn, pfx##20, sfx),					\
-	PORT_1(fn, pfx##210, sfx),	PORT_1(fn, pfx##211, sfx)
-
-enum {
-	PINMUX_RESERVED = 0,
-
-	/* PORT0_DATA -> PORT211_DATA */
-	PINMUX_DATA_BEGIN,
-	PORT_ALL(DATA),
-	PINMUX_DATA_END,
-
-	/* PORT0_IN -> PORT211_IN */
-	PINMUX_INPUT_BEGIN,
-	PORT_ALL(IN),
-	PINMUX_INPUT_END,
-
-	/* PORT0_IN_PU -> PORT211_IN_PU */
-	PINMUX_INPUT_PULLUP_BEGIN,
-	PORT_ALL(IN_PU),
-	PINMUX_INPUT_PULLUP_END,
-
-	/* PORT0_IN_PD -> PORT211_IN_PD */
-	PINMUX_INPUT_PULLDOWN_BEGIN,
-	PORT_ALL(IN_PD),
-	PINMUX_INPUT_PULLDOWN_END,
-
-	/* PORT0_OUT -> PORT211_OUT */
-	PINMUX_OUTPUT_BEGIN,
-	PORT_ALL(OUT),
-	PINMUX_OUTPUT_END,
-
-	PINMUX_FUNCTION_BEGIN,
-	PORT_ALL(FN_IN),	/* PORT0_FN_IN -> PORT211_FN_IN */
-	PORT_ALL(FN_OUT),	/* PORT0_FN_OUT -> PORT211_FN_OUT */
-	PORT_ALL(FN0),		/* PORT0_FN0 -> PORT211_FN0 */
-	PORT_ALL(FN1),		/* PORT0_FN1 -> PORT211_FN1 */
-	PORT_ALL(FN2),		/* PORT0_FN2 -> PORT211_FN2 */
-	PORT_ALL(FN3),		/* PORT0_FN3 -> PORT211_FN3 */
-	PORT_ALL(FN4),		/* PORT0_FN4 -> PORT211_FN4 */
-	PORT_ALL(FN5),		/* PORT0_FN5 -> PORT211_FN5 */
-	PORT_ALL(FN6),		/* PORT0_FN6 -> PORT211_FN6 */
-	PORT_ALL(FN7),		/* PORT0_FN7 -> PORT211_FN7 */
-
-	MSEL1CR_31_0,	MSEL1CR_31_1,
-	MSEL1CR_30_0,	MSEL1CR_30_1,
-	MSEL1CR_29_0,	MSEL1CR_29_1,
-	MSEL1CR_28_0,	MSEL1CR_28_1,
-	MSEL1CR_27_0,	MSEL1CR_27_1,
-	MSEL1CR_26_0,	MSEL1CR_26_1,
-	MSEL1CR_16_0,	MSEL1CR_16_1,
-	MSEL1CR_15_0,	MSEL1CR_15_1,
-	MSEL1CR_14_0,	MSEL1CR_14_1,
-	MSEL1CR_13_0,	MSEL1CR_13_1,
-	MSEL1CR_12_0,	MSEL1CR_12_1,
-	MSEL1CR_9_0,	MSEL1CR_9_1,
-	MSEL1CR_7_0,	MSEL1CR_7_1,
-	MSEL1CR_6_0,	MSEL1CR_6_1,
-	MSEL1CR_5_0,	MSEL1CR_5_1,
-	MSEL1CR_4_0,	MSEL1CR_4_1,
-	MSEL1CR_3_0,	MSEL1CR_3_1,
-	MSEL1CR_2_0,	MSEL1CR_2_1,
-	MSEL1CR_0_0,	MSEL1CR_0_1,
-
-	MSEL3CR_15_0,	MSEL3CR_15_1, /* Trace / Debug ? */
-	MSEL3CR_6_0,	MSEL3CR_6_1,
-
-	MSEL4CR_19_0,	MSEL4CR_19_1,
-	MSEL4CR_18_0,	MSEL4CR_18_1,
-	MSEL4CR_15_0,	MSEL4CR_15_1,
-	MSEL4CR_10_0,	MSEL4CR_10_1,
-	MSEL4CR_6_0,	MSEL4CR_6_1,
-	MSEL4CR_4_0,	MSEL4CR_4_1,
-	MSEL4CR_1_0,	MSEL4CR_1_1,
-
-	MSEL5CR_31_0,	MSEL5CR_31_1, /* irq/fiq output */
-	MSEL5CR_30_0,	MSEL5CR_30_1,
-	MSEL5CR_29_0,	MSEL5CR_29_1,
-	MSEL5CR_27_0,	MSEL5CR_27_1,
-	MSEL5CR_25_0,	MSEL5CR_25_1,
-	MSEL5CR_23_0,	MSEL5CR_23_1,
-	MSEL5CR_21_0,	MSEL5CR_21_1,
-	MSEL5CR_19_0,	MSEL5CR_19_1,
-	MSEL5CR_17_0,	MSEL5CR_17_1,
-	MSEL5CR_15_0,	MSEL5CR_15_1,
-	MSEL5CR_14_0,	MSEL5CR_14_1,
-	MSEL5CR_13_0,	MSEL5CR_13_1,
-	MSEL5CR_12_0,	MSEL5CR_12_1,
-	MSEL5CR_11_0,	MSEL5CR_11_1,
-	MSEL5CR_10_0,	MSEL5CR_10_1,
-	MSEL5CR_8_0,	MSEL5CR_8_1,
-	MSEL5CR_7_0,	MSEL5CR_7_1,
-	MSEL5CR_6_0,	MSEL5CR_6_1,
-	MSEL5CR_5_0,	MSEL5CR_5_1,
-	MSEL5CR_4_0,	MSEL5CR_4_1,
-	MSEL5CR_3_0,	MSEL5CR_3_1,
-	MSEL5CR_2_0,	MSEL5CR_2_1,
-	MSEL5CR_0_0,	MSEL5CR_0_1,
-	PINMUX_FUNCTION_END,
-
-	PINMUX_MARK_BEGIN,
-
-	/* IRQ */
-	IRQ0_PORT2_MARK,	IRQ0_PORT13_MARK,
-	IRQ1_MARK,
-	IRQ2_PORT11_MARK,	IRQ2_PORT12_MARK,
-	IRQ3_PORT10_MARK,	IRQ3_PORT14_MARK,
-	IRQ4_PORT15_MARK,	IRQ4_PORT172_MARK,
-	IRQ5_PORT0_MARK,	IRQ5_PORT1_MARK,
-	IRQ6_PORT121_MARK,	IRQ6_PORT173_MARK,
-	IRQ7_PORT120_MARK,	IRQ7_PORT209_MARK,
-	IRQ8_MARK,
-	IRQ9_PORT118_MARK,	IRQ9_PORT210_MARK,
-	IRQ10_MARK,
-	IRQ11_MARK,
-	IRQ12_PORT42_MARK,	IRQ12_PORT97_MARK,
-	IRQ13_PORT64_MARK,	IRQ13_PORT98_MARK,
-	IRQ14_PORT63_MARK,	IRQ14_PORT99_MARK,
-	IRQ15_PORT62_MARK,	IRQ15_PORT100_MARK,
-	IRQ16_PORT68_MARK,	IRQ16_PORT211_MARK,
-	IRQ17_MARK,
-	IRQ18_MARK,
-	IRQ19_MARK,
-	IRQ20_MARK,
-	IRQ21_MARK,
-	IRQ22_MARK,
-	IRQ23_MARK,
-	IRQ24_MARK,
-	IRQ25_MARK,
-	IRQ26_PORT58_MARK,	IRQ26_PORT81_MARK,
-	IRQ27_PORT57_MARK,	IRQ27_PORT168_MARK,
-	IRQ28_PORT56_MARK,	IRQ28_PORT169_MARK,
-	IRQ29_PORT50_MARK,	IRQ29_PORT170_MARK,
-	IRQ30_PORT49_MARK,	IRQ30_PORT171_MARK,
-	IRQ31_PORT41_MARK,	IRQ31_PORT167_MARK,
-
-	/* Function */
-
-	/* DBGT */
-	DBGMDT2_MARK,	DBGMDT1_MARK,	DBGMDT0_MARK,
-	DBGMD10_MARK,	DBGMD11_MARK,	DBGMD20_MARK,
-	DBGMD21_MARK,
-
-	/* FSI-A */
-	FSIAISLD_PORT0_MARK,	/* FSIAISLD Port 0/5 */
-	FSIAISLD_PORT5_MARK,
-	FSIASPDIF_PORT9_MARK,	/* FSIASPDIF Port 9/18 */
-	FSIASPDIF_PORT18_MARK,
-	FSIAOSLD1_MARK,	FSIAOSLD2_MARK,	FSIAOLR_MARK,
-	FSIAOBT_MARK,	FSIAOSLD_MARK,	FSIAOMC_MARK,
-	FSIACK_MARK,	FSIAILR_MARK,	FSIAIBT_MARK,
-
-	/* FSI-B */
-	FSIBCK_MARK,
-
-	/* FMSI */
-	FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
-	FMSISLD_PORT6_MARK,
-	FMSIILR_MARK,	FMSIIBT_MARK,	FMSIOLR_MARK,	FMSIOBT_MARK,
-	FMSICK_MARK,	FMSOILR_MARK,	FMSOIBT_MARK,	FMSOOLR_MARK,
-	FMSOOBT_MARK,	FMSOSLD_MARK,	FMSOCK_MARK,
-
-	/* SCIFA0 */
-	SCIFA0_SCK_MARK,	SCIFA0_CTS_MARK,	SCIFA0_RTS_MARK,
-	SCIFA0_RXD_MARK,	SCIFA0_TXD_MARK,
-
-	/* SCIFA1 */
-	SCIFA1_CTS_MARK,	SCIFA1_SCK_MARK,	SCIFA1_RXD_MARK,
-	SCIFA1_TXD_MARK,	SCIFA1_RTS_MARK,
-
-	/* SCIFA2 */
-	SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
-	SCIFA2_SCK_PORT199_MARK,
-	SCIFA2_RXD_MARK,	SCIFA2_TXD_MARK,
-	SCIFA2_CTS_MARK,	SCIFA2_RTS_MARK,
-
-	/* SCIFA3 */
-	SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
-	SCIFA3_SCK_PORT116_MARK,
-	SCIFA3_CTS_PORT117_MARK,
-	SCIFA3_RXD_PORT174_MARK,
-	SCIFA3_TXD_PORT175_MARK,
-
-	SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
-	SCIFA3_SCK_PORT158_MARK,
-	SCIFA3_CTS_PORT162_MARK,
-	SCIFA3_RXD_PORT159_MARK,
-	SCIFA3_TXD_PORT160_MARK,
-
-	/* SCIFA4 */
-	SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
-	SCIFA4_TXD_PORT13_MARK,
-
-	SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
-	SCIFA4_TXD_PORT203_MARK,
-
-	SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
-	SCIFA4_TXD_PORT93_MARK,
-
-	SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
-	SCIFA4_SCK_PORT205_MARK,
-
-	/* SCIFA5 */
-	SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
-	SCIFA5_RXD_PORT10_MARK,
-
-	SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
-	SCIFA5_TXD_PORT208_MARK,
-
-	SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
-	SCIFA5_RXD_PORT92_MARK,
-
-	SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
-	SCIFA5_SCK_PORT206_MARK,
-
-	/* SCIFA6 */
-	SCIFA6_SCK_MARK,	SCIFA6_RXD_MARK,	SCIFA6_TXD_MARK,
-
-	/* SCIFA7 */
-	SCIFA7_TXD_MARK,	SCIFA7_RXD_MARK,
-
-	/* SCIFAB */
-	SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
-	SCIFB_RXD_PORT191_MARK,
-	SCIFB_TXD_PORT192_MARK,
-	SCIFB_RTS_PORT186_MARK,
-	SCIFB_CTS_PORT187_MARK,
-
-	SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
-	SCIFB_RXD_PORT3_MARK,
-	SCIFB_TXD_PORT4_MARK,
-	SCIFB_RTS_PORT172_MARK,
-	SCIFB_CTS_PORT173_MARK,
-
-	/* LCD0 */
-	LCDC0_SELECT_MARK,
-
-	LCD0_D0_MARK,	LCD0_D1_MARK,	LCD0_D2_MARK,	LCD0_D3_MARK,
-	LCD0_D4_MARK,	LCD0_D5_MARK,	LCD0_D6_MARK,	LCD0_D7_MARK,
-	LCD0_D8_MARK,	LCD0_D9_MARK,	LCD0_D10_MARK,	LCD0_D11_MARK,
-	LCD0_D12_MARK,	LCD0_D13_MARK,	LCD0_D14_MARK,	LCD0_D15_MARK,
-	LCD0_D16_MARK,	LCD0_D17_MARK,
-	LCD0_DON_MARK,	LCD0_VCPWC_MARK,	LCD0_VEPWC_MARK,
-	LCD0_DCK_MARK,	LCD0_VSYN_MARK,	/* for RGB */
-	LCD0_HSYN_MARK,	LCD0_DISP_MARK,	/* for RGB */
-	LCD0_WR_MARK,	LCD0_RD_MARK,	/* for SYS */
-	LCD0_CS_MARK,	LCD0_RS_MARK,	/* for SYS */
-
-	LCD0_D21_PORT158_MARK,	LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
-	LCD0_D22_PORT160_MARK,	LCD0_D20_PORT161_MARK,
-	LCD0_D19_PORT162_MARK,	LCD0_D18_PORT163_MARK,
-	LCD0_LCLK_PORT165_MARK,
-
-	LCD0_D18_PORT40_MARK,	LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
-	LCD0_D23_PORT1_MARK,	LCD0_D21_PORT2_MARK,
-	LCD0_D20_PORT3_MARK,	LCD0_D19_PORT4_MARK,
-	LCD0_LCLK_PORT102_MARK,
-
-	/* LCD1 */
-	LCDC1_SELECT_MARK,
-
-	LCD1_D0_MARK,	LCD1_D1_MARK,	LCD1_D2_MARK,	LCD1_D3_MARK,
-	LCD1_D4_MARK,	LCD1_D5_MARK,	LCD1_D6_MARK,	LCD1_D7_MARK,
-	LCD1_D8_MARK,	LCD1_D9_MARK,	LCD1_D10_MARK,	LCD1_D11_MARK,
-	LCD1_D12_MARK,	LCD1_D13_MARK,	LCD1_D14_MARK,	LCD1_D15_MARK,
-	LCD1_D16_MARK,	LCD1_D17_MARK,	LCD1_D18_MARK,	LCD1_D19_MARK,
-	LCD1_D20_MARK,	LCD1_D21_MARK,	LCD1_D22_MARK,	LCD1_D23_MARK,
-	LCD1_DON_MARK,	LCD1_VCPWC_MARK,
-	LCD1_LCLK_MARK,	LCD1_VEPWC_MARK,
-
-	LCD1_DCK_MARK,	LCD1_VSYN_MARK,	/* for RGB */
-	LCD1_HSYN_MARK,	LCD1_DISP_MARK,	/* for RGB */
-	LCD1_RS_MARK,	LCD1_CS_MARK,	/* for SYS */
-	LCD1_RD_MARK,	LCD1_WR_MARK,	/* for SYS */
-
-	/* RSPI */
-	RSPI_SSL0_A_MARK,	RSPI_SSL1_A_MARK,	RSPI_SSL2_A_MARK,
-	RSPI_SSL3_A_MARK,	RSPI_CK_A_MARK,		RSPI_MOSI_A_MARK,
-	RSPI_MISO_A_MARK,
-
-	/* VIO CKO */
-	VIO_CKO1_MARK, /* needs fixup */
-	VIO_CKO2_MARK,
-	VIO_CKO_1_MARK,
-	VIO_CKO_MARK,
-
-	/* VIO0 */
-	VIO0_D0_MARK,	VIO0_D1_MARK,	VIO0_D2_MARK,	VIO0_D3_MARK,
-	VIO0_D4_MARK,	VIO0_D5_MARK,	VIO0_D6_MARK,	VIO0_D7_MARK,
-	VIO0_D8_MARK,	VIO0_D9_MARK,	VIO0_D10_MARK,	VIO0_D11_MARK,
-	VIO0_D12_MARK,	VIO0_VD_MARK,	VIO0_HD_MARK,	VIO0_CLK_MARK,
-	VIO0_FIELD_MARK,
-
-	VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
-	VIO0_D14_PORT25_MARK,
-	VIO0_D15_PORT24_MARK,
-
-	VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
-	VIO0_D14_PORT95_MARK,
-	VIO0_D15_PORT96_MARK,
-
-	/* VIO1 */
-	VIO1_D0_MARK,	VIO1_D1_MARK,	VIO1_D2_MARK,	VIO1_D3_MARK,
-	VIO1_D4_MARK,	VIO1_D5_MARK,	VIO1_D6_MARK,	VIO1_D7_MARK,
-	VIO1_VD_MARK,	VIO1_HD_MARK,	VIO1_CLK_MARK,	VIO1_FIELD_MARK,
-
-	/* TPU0 */
-	TPU0TO0_MARK,	TPU0TO1_MARK,	TPU0TO3_MARK,
-	TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
-	TPU0TO2_PORT202_MARK,
-
-	/* SSP1 0 */
-	STP0_IPD0_MARK,	STP0_IPD1_MARK,	STP0_IPD2_MARK,	STP0_IPD3_MARK,
-	STP0_IPD4_MARK,	STP0_IPD5_MARK,	STP0_IPD6_MARK,	STP0_IPD7_MARK,
-	STP0_IPEN_MARK,	STP0_IPCLK_MARK,	STP0_IPSYNC_MARK,
-
-	/* SSP1 1 */
-	STP1_IPD1_MARK,	STP1_IPD2_MARK,	STP1_IPD3_MARK,	STP1_IPD4_MARK,
-	STP1_IPD5_MARK,	STP1_IPD6_MARK,	STP1_IPD7_MARK,	STP1_IPCLK_MARK,
-	STP1_IPSYNC_MARK,
-
-	STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
-	STP1_IPEN_PORT187_MARK,
-
-	STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
-	STP1_IPEN_PORT193_MARK,
-
-	/* SIM */
-	SIM_RST_MARK,	SIM_CLK_MARK,
-	SIM_D_PORT22_MARK, /* SIM_D  Port 22/199 */
-	SIM_D_PORT199_MARK,
-
-	/* SDHI0 */
-	SDHI0_D0_MARK,	SDHI0_D1_MARK,	SDHI0_D2_MARK,	SDHI0_D3_MARK,
-	SDHI0_CD_MARK,	SDHI0_WP_MARK,	SDHI0_CMD_MARK,	SDHI0_CLK_MARK,
-
-	/* SDHI1 */
-	SDHI1_D0_MARK,	SDHI1_D1_MARK,	SDHI1_D2_MARK,	SDHI1_D3_MARK,
-	SDHI1_CD_MARK,	SDHI1_WP_MARK,	SDHI1_CMD_MARK,	SDHI1_CLK_MARK,
-
-	/* SDHI2 */
-	SDHI2_D0_MARK,	SDHI2_D1_MARK,	SDHI2_D2_MARK,	SDHI2_D3_MARK,
-	SDHI2_CLK_MARK,	SDHI2_CMD_MARK,
-
-	SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
-	SDHI2_WP_PORT25_MARK,
-
-	SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
-	SDHI2_CD_PORT202_MARK,
-
-	/* MSIOF2 */
-	MSIOF2_TXD_MARK,	MSIOF2_RXD_MARK,	MSIOF2_TSCK_MARK,
-	MSIOF2_SS2_MARK,	MSIOF2_TSYNC_MARK,	MSIOF2_SS1_MARK,
-	MSIOF2_MCK1_MARK,	MSIOF2_MCK0_MARK,	MSIOF2_RSYNC_MARK,
-	MSIOF2_RSCK_MARK,
-
-	/* KEYSC */
-	KEYIN4_MARK,	KEYIN5_MARK,	KEYIN6_MARK,	KEYIN7_MARK,
-	KEYOUT0_MARK,	KEYOUT1_MARK,	KEYOUT2_MARK,	KEYOUT3_MARK,
-	KEYOUT4_MARK,	KEYOUT5_MARK,	KEYOUT6_MARK,	KEYOUT7_MARK,
-
-	KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
-	KEYIN1_PORT44_MARK,
-	KEYIN2_PORT45_MARK,
-	KEYIN3_PORT46_MARK,
-
-	KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
-	KEYIN1_PORT57_MARK,
-	KEYIN2_PORT56_MARK,
-	KEYIN3_PORT55_MARK,
-
-	/* VOU */
-	DV_D0_MARK,	DV_D1_MARK,	DV_D2_MARK,	DV_D3_MARK,
-	DV_D4_MARK,	DV_D5_MARK,	DV_D6_MARK,	DV_D7_MARK,
-	DV_D8_MARK,	DV_D9_MARK,	DV_D10_MARK,	DV_D11_MARK,
-	DV_D12_MARK,	DV_D13_MARK,	DV_D14_MARK,	DV_D15_MARK,
-	DV_CLK_MARK,	DV_VSYNC_MARK,	DV_HSYNC_MARK,
-
-	/* MEMC */
-	MEMC_AD0_MARK,	MEMC_AD1_MARK,	MEMC_AD2_MARK,	MEMC_AD3_MARK,
-	MEMC_AD4_MARK,	MEMC_AD5_MARK,	MEMC_AD6_MARK,	MEMC_AD7_MARK,
-	MEMC_AD8_MARK,	MEMC_AD9_MARK,	MEMC_AD10_MARK,	MEMC_AD11_MARK,
-	MEMC_AD12_MARK,	MEMC_AD13_MARK,	MEMC_AD14_MARK,	MEMC_AD15_MARK,
-	MEMC_CS0_MARK,	MEMC_INT_MARK,	MEMC_NWE_MARK,	MEMC_NOE_MARK,
-
-	MEMC_CS1_MARK, /* MSEL4CR_6_0 */
-	MEMC_ADV_MARK,
-	MEMC_WAIT_MARK,
-	MEMC_BUSCLK_MARK,
-
-	MEMC_A1_MARK, /* MSEL4CR_6_1 */
-	MEMC_DREQ0_MARK,
-	MEMC_DREQ1_MARK,
-	MEMC_A0_MARK,
-
-	/* MMC */
-	MMC0_D0_PORT68_MARK,	MMC0_D1_PORT69_MARK,	MMC0_D2_PORT70_MARK,
-	MMC0_D3_PORT71_MARK,	MMC0_D4_PORT72_MARK,	MMC0_D5_PORT73_MARK,
-	MMC0_D6_PORT74_MARK,	MMC0_D7_PORT75_MARK,	MMC0_CLK_PORT66_MARK,
-	MMC0_CMD_PORT67_MARK,	/* MSEL4CR_15_0 */
-
-	MMC1_D0_PORT149_MARK,	MMC1_D1_PORT148_MARK,	MMC1_D2_PORT147_MARK,
-	MMC1_D3_PORT146_MARK,	MMC1_D4_PORT145_MARK,	MMC1_D5_PORT144_MARK,
-	MMC1_D6_PORT143_MARK,	MMC1_D7_PORT142_MARK,	MMC1_CLK_PORT103_MARK,
-	MMC1_CMD_PORT104_MARK,	/* MSEL4CR_15_1 */
-
-	/* MSIOF0 */
-	MSIOF0_SS1_MARK,	MSIOF0_SS2_MARK,	MSIOF0_RXD_MARK,
-	MSIOF0_TXD_MARK,	MSIOF0_MCK0_MARK,	MSIOF0_MCK1_MARK,
-	MSIOF0_RSYNC_MARK,	MSIOF0_RSCK_MARK,	MSIOF0_TSCK_MARK,
-	MSIOF0_TSYNC_MARK,
-
-	/* MSIOF1 */
-	MSIOF1_RSCK_MARK,	MSIOF1_RSYNC_MARK,
-	MSIOF1_MCK0_MARK,	MSIOF1_MCK1_MARK,
-
-	MSIOF1_SS2_PORT116_MARK,	MSIOF1_SS1_PORT117_MARK,
-	MSIOF1_RXD_PORT118_MARK,	MSIOF1_TXD_PORT119_MARK,
-	MSIOF1_TSYNC_PORT120_MARK,
-	MSIOF1_TSCK_PORT121_MARK,	/* MSEL4CR_10_0 */
-
-	MSIOF1_SS1_PORT67_MARK,		MSIOF1_TSCK_PORT72_MARK,
-	MSIOF1_TSYNC_PORT73_MARK,	MSIOF1_TXD_PORT74_MARK,
-	MSIOF1_RXD_PORT75_MARK,
-	MSIOF1_SS2_PORT202_MARK,	/* MSEL4CR_10_1 */
-
-	/* GPIO */
-	GPO0_MARK,	GPI0_MARK,	GPO1_MARK,	GPI1_MARK,
-
-	/* USB0 */
-	USB0_OCI_MARK,	USB0_PPON_MARK,	VBUS_MARK,
-
-	/* USB1 */
-	USB1_OCI_MARK,	USB1_PPON_MARK,
-
-	/* BBIF1 */
-	BBIF1_RXD_MARK,		BBIF1_TXD_MARK,		BBIF1_TSYNC_MARK,
-	BBIF1_TSCK_MARK,	BBIF1_RSCK_MARK,	BBIF1_RSYNC_MARK,
-	BBIF1_FLOW_MARK,	BBIF1_RX_FLOW_N_MARK,
-
-	/* BBIF2 */
-	BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
-	BBIF2_RXD2_PORT60_MARK,
-	BBIF2_TSYNC2_PORT6_MARK,
-	BBIF2_TSCK2_PORT59_MARK,
-
-	BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
-	BBIF2_TXD2_PORT183_MARK,
-	BBIF2_TSCK2_PORT89_MARK,
-	BBIF2_TSYNC2_PORT184_MARK,
-
-	/* BSC / FLCTL / PCMCIA */
-	CS0_MARK,	CS2_MARK,	CS4_MARK,
-	CS5B_MARK,	CS6A_MARK,
-	CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
-	CS5A_PORT19_MARK,
-	IOIS16_MARK, /* ? */
-
-	A0_MARK,	A1_MARK,	A2_MARK,	A3_MARK,
-	A4_FOE_MARK,	/* share with FLCTL */
-	A5_FCDE_MARK,	/* share with FLCTL */
-	A6_MARK,	A7_MARK,	A8_MARK,	A9_MARK,
-	A10_MARK,	A11_MARK,	A12_MARK,	A13_MARK,
-	A14_MARK,	A15_MARK,	A16_MARK,	A17_MARK,
-	A18_MARK,	A19_MARK,	A20_MARK,	A21_MARK,
-	A22_MARK,	A23_MARK,	A24_MARK,	A25_MARK,
-	A26_MARK,
-
-	D0_NAF0_MARK,	D1_NAF1_MARK,	D2_NAF2_MARK,	/* share with FLCTL */
-	D3_NAF3_MARK,	D4_NAF4_MARK,	D5_NAF5_MARK,	/* share with FLCTL */
-	D6_NAF6_MARK,	D7_NAF7_MARK,	D8_NAF8_MARK,	/* share with FLCTL */
-	D9_NAF9_MARK,	D10_NAF10_MARK,	D11_NAF11_MARK,	/* share with FLCTL */
-	D12_NAF12_MARK,	D13_NAF13_MARK,	D14_NAF14_MARK,	/* share with FLCTL */
-	D15_NAF15_MARK,					/* share with FLCTL */
-	D16_MARK,	D17_MARK,	D18_MARK,	D19_MARK,
-	D20_MARK,	D21_MARK,	D22_MARK,	D23_MARK,
-	D24_MARK,	D25_MARK,	D26_MARK,	D27_MARK,
-	D28_MARK,	D29_MARK,	D30_MARK,	D31_MARK,
-
-	WE0_FWE_MARK,	/* share with FLCTL */
-	WE1_MARK,
-	WE2_ICIORD_MARK,	/* share with PCMCIA */
-	WE3_ICIOWR_MARK,	/* share with PCMCIA */
-	CKO_MARK,	BS_MARK,	RDWR_MARK,
-	RD_FSC_MARK,	/* share with FLCTL */
-	WAIT_PORT177_MARK, /* WAIT Port 90/177 */
-	WAIT_PORT90_MARK,
-
-	FCE0_MARK,	FCE1_MARK,	FRB_MARK, /* FLCTL */
-
-	/* IRDA */
-	IRDA_FIRSEL_MARK,	IRDA_IN_MARK,	IRDA_OUT_MARK,
-
-	/* ATAPI */
-	IDE_D0_MARK,	IDE_D1_MARK,	IDE_D2_MARK,	IDE_D3_MARK,
-	IDE_D4_MARK,	IDE_D5_MARK,	IDE_D6_MARK,	IDE_D7_MARK,
-	IDE_D8_MARK,	IDE_D9_MARK,	IDE_D10_MARK,	IDE_D11_MARK,
-	IDE_D12_MARK,	IDE_D13_MARK,	IDE_D14_MARK,	IDE_D15_MARK,
-	IDE_A0_MARK,	IDE_A1_MARK,	IDE_A2_MARK,	IDE_CS0_MARK,
-	IDE_CS1_MARK,	IDE_IOWR_MARK,	IDE_IORD_MARK,	IDE_IORDY_MARK,
-	IDE_INT_MARK,		IDE_RST_MARK,		IDE_DIRECTION_MARK,
-	IDE_EXBUF_ENB_MARK,	IDE_IODACK_MARK,	IDE_IODREQ_MARK,
-
-	/* RMII */
-	RMII_CRS_DV_MARK,	RMII_RX_ER_MARK,	RMII_RXD0_MARK,
-	RMII_RXD1_MARK,		RMII_TX_EN_MARK,	RMII_TXD0_MARK,
-	RMII_MDC_MARK,		RMII_TXD1_MARK,		RMII_MDIO_MARK,
-	RMII_REF50CK_MARK,	/* for RMII */
-	RMII_REF125CK_MARK,	/* for GMII */
-
-	/* GEther */
-	ET_TX_CLK_MARK,	ET_TX_EN_MARK,	ET_ETXD0_MARK,	ET_ETXD1_MARK,
-	ET_ETXD2_MARK,	ET_ETXD3_MARK,
-	ET_ETXD4_MARK,	ET_ETXD5_MARK, /* for GEther */
-	ET_ETXD6_MARK,	ET_ETXD7_MARK, /* for GEther */
-	ET_COL_MARK,	ET_TX_ER_MARK,	ET_RX_CLK_MARK,	ET_RX_DV_MARK,
-	ET_ERXD0_MARK,	ET_ERXD1_MARK,	ET_ERXD2_MARK,	ET_ERXD3_MARK,
-	ET_ERXD4_MARK,	ET_ERXD5_MARK, /* for GEther */
-	ET_ERXD6_MARK,	ET_ERXD7_MARK, /* for GEther */
-	ET_RX_ER_MARK,	ET_CRS_MARK,		ET_MDC_MARK,	ET_MDIO_MARK,
-	ET_LINK_MARK,	ET_PHY_INT_MARK,	ET_WOL_MARK,	ET_GTX_CLK_MARK,
-
-	/* DMA0 */
-	DREQ0_MARK,	DACK0_MARK,
-
-	/* DMA1 */
-	DREQ1_MARK,	DACK1_MARK,
-
-	/* SYSC */
-	RESETOUTS_MARK,		RESETP_PULLUP_MARK,	RESETP_PLAIN_MARK,
-
-	/* IRREM */
-	IROUT_MARK,
-
-	/* SDENC */
-	SDENC_CPG_MARK,		SDENC_DV_CLKI_MARK,
-
-	/* HDMI */
-	HDMI_HPD_MARK, HDMI_CEC_MARK,
-
-	/* DEBUG */
-	EDEBGREQ_PULLUP_MARK,	/* for JTAG */
-	EDEBGREQ_PULLDOWN_MARK,
-
-	TRACEAUD_FROM_VIO_MARK,	/* for TRACE/AUD */
-	TRACEAUD_FROM_LCDC0_MARK,
-	TRACEAUD_FROM_MEMC_MARK,
-
-	PINMUX_MARK_END,
-};
-
-static pinmux_enum_t pinmux_data[] = {
-	/* specify valid pin states for each pin in GPIO mode */
-
-	/* I/O and Pull U/D */
-	PORT_DATA_IO_PD(0),		PORT_DATA_IO_PD(1),
-	PORT_DATA_IO_PD(2),		PORT_DATA_IO_PD(3),
-	PORT_DATA_IO_PD(4),		PORT_DATA_IO_PD(5),
-	PORT_DATA_IO_PD(6),		PORT_DATA_IO(7),
-	PORT_DATA_IO(8),		PORT_DATA_IO(9),
-
-	PORT_DATA_IO_PD(10),		PORT_DATA_IO_PD(11),
-	PORT_DATA_IO_PD(12),		PORT_DATA_IO_PU_PD(13),
-	PORT_DATA_IO_PD(14),		PORT_DATA_IO_PD(15),
-	PORT_DATA_IO_PD(16),		PORT_DATA_IO_PD(17),
-	PORT_DATA_IO(18),		PORT_DATA_IO_PU(19),
-
-	PORT_DATA_IO_PU_PD(20),		PORT_DATA_IO_PD(21),
-	PORT_DATA_IO_PU_PD(22),		PORT_DATA_IO(23),
-	PORT_DATA_IO_PU(24),		PORT_DATA_IO_PU(25),
-	PORT_DATA_IO_PU(26),		PORT_DATA_IO_PU(27),
-	PORT_DATA_IO_PU(28),		PORT_DATA_IO_PU(29),
-
-	PORT_DATA_IO_PU(30),		PORT_DATA_IO_PD(31),
-	PORT_DATA_IO_PD(32),		PORT_DATA_IO_PD(33),
-	PORT_DATA_IO_PD(34),		PORT_DATA_IO_PU(35),
-	PORT_DATA_IO_PU(36),		PORT_DATA_IO_PD(37),
-	PORT_DATA_IO_PU(38),		PORT_DATA_IO_PD(39),
-
-	PORT_DATA_IO_PU_PD(40),		PORT_DATA_IO_PD(41),
-	PORT_DATA_IO_PD(42),		PORT_DATA_IO_PU_PD(43),
-	PORT_DATA_IO_PU_PD(44),		PORT_DATA_IO_PU_PD(45),
-	PORT_DATA_IO_PU_PD(46),		PORT_DATA_IO_PU_PD(47),
-	PORT_DATA_IO_PU_PD(48),		PORT_DATA_IO_PU_PD(49),
-
-	PORT_DATA_IO_PU_PD(50),		PORT_DATA_IO_PD(51),
-	PORT_DATA_IO_PD(52),		PORT_DATA_IO_PD(53),
-	PORT_DATA_IO_PD(54),		PORT_DATA_IO_PU_PD(55),
-	PORT_DATA_IO_PU_PD(56),		PORT_DATA_IO_PU_PD(57),
-	PORT_DATA_IO_PU_PD(58),		PORT_DATA_IO_PU_PD(59),
-
-	PORT_DATA_IO_PU_PD(60),		PORT_DATA_IO_PD(61),
-	PORT_DATA_IO_PD(62),		PORT_DATA_IO_PD(63),
-	PORT_DATA_IO_PD(64),		PORT_DATA_IO_PD(65),
-	PORT_DATA_IO_PU_PD(66),		PORT_DATA_IO_PU_PD(67),
-	PORT_DATA_IO_PU_PD(68),		PORT_DATA_IO_PU_PD(69),
-
-	PORT_DATA_IO_PU_PD(70),		PORT_DATA_IO_PU_PD(71),
-	PORT_DATA_IO_PU_PD(72),		PORT_DATA_IO_PU_PD(73),
-	PORT_DATA_IO_PU_PD(74),		PORT_DATA_IO_PU_PD(75),
-	PORT_DATA_IO_PU_PD(76),		PORT_DATA_IO_PU_PD(77),
-	PORT_DATA_IO_PU_PD(78),		PORT_DATA_IO_PU_PD(79),
-
-	PORT_DATA_IO_PU_PD(80),		PORT_DATA_IO_PU_PD(81),
-	PORT_DATA_IO(82),		PORT_DATA_IO_PU_PD(83),
-	PORT_DATA_IO(84),		PORT_DATA_IO_PD(85),
-	PORT_DATA_IO_PD(86),		PORT_DATA_IO_PD(87),
-	PORT_DATA_IO_PD(88),		PORT_DATA_IO_PD(89),
-
-	PORT_DATA_IO_PD(90),		PORT_DATA_IO_PU_PD(91),
-	PORT_DATA_IO_PU_PD(92),		PORT_DATA_IO_PU_PD(93),
-	PORT_DATA_IO_PU_PD(94),		PORT_DATA_IO_PU_PD(95),
-	PORT_DATA_IO_PU_PD(96),		PORT_DATA_IO_PU_PD(97),
-	PORT_DATA_IO_PU_PD(98),		PORT_DATA_IO_PU_PD(99),
-
-	PORT_DATA_IO_PU_PD(100),	PORT_DATA_IO(101),
-	PORT_DATA_IO_PU(102),		PORT_DATA_IO_PU_PD(103),
-	PORT_DATA_IO_PU(104),		PORT_DATA_IO_PU(105),
-	PORT_DATA_IO_PU_PD(106),	PORT_DATA_IO(107),
-	PORT_DATA_IO(108),		PORT_DATA_IO(109),
-
-	PORT_DATA_IO(110),		PORT_DATA_IO(111),
-	PORT_DATA_IO(112),		PORT_DATA_IO(113),
-	PORT_DATA_IO_PU_PD(114),	PORT_DATA_IO(115),
-	PORT_DATA_IO_PD(116),		PORT_DATA_IO_PD(117),
-	PORT_DATA_IO_PD(118),		PORT_DATA_IO_PD(119),
-
-	PORT_DATA_IO_PD(120),		PORT_DATA_IO_PD(121),
-	PORT_DATA_IO_PD(122),		PORT_DATA_IO_PD(123),
-	PORT_DATA_IO_PD(124),		PORT_DATA_IO(125),
-	PORT_DATA_IO(126),		PORT_DATA_IO(127),
-	PORT_DATA_IO(128),		PORT_DATA_IO(129),
-
-	PORT_DATA_IO(130),		PORT_DATA_IO(131),
-	PORT_DATA_IO(132),		PORT_DATA_IO(133),
-	PORT_DATA_IO(134),		PORT_DATA_IO(135),
-	PORT_DATA_IO(136),		PORT_DATA_IO(137),
-	PORT_DATA_IO(138),		PORT_DATA_IO(139),
-
-	PORT_DATA_IO(140),		PORT_DATA_IO(141),
-	PORT_DATA_IO_PU(142),		PORT_DATA_IO_PU(143),
-	PORT_DATA_IO_PU(144),		PORT_DATA_IO_PU(145),
-	PORT_DATA_IO_PU(146),		PORT_DATA_IO_PU(147),
-	PORT_DATA_IO_PU(148),		PORT_DATA_IO_PU(149),
-
-	PORT_DATA_IO_PU(150),		PORT_DATA_IO_PU(151),
-	PORT_DATA_IO_PU(152),		PORT_DATA_IO_PU(153),
-	PORT_DATA_IO_PU(154),		PORT_DATA_IO_PU(155),
-	PORT_DATA_IO_PU(156),		PORT_DATA_IO_PU(157),
-	PORT_DATA_IO_PD(158),		PORT_DATA_IO_PD(159),
-
-	PORT_DATA_IO_PU_PD(160),	PORT_DATA_IO_PD(161),
-	PORT_DATA_IO_PD(162),		PORT_DATA_IO_PD(163),
-	PORT_DATA_IO_PD(164),		PORT_DATA_IO_PD(165),
-	PORT_DATA_IO_PU(166),		PORT_DATA_IO_PU(167),
-	PORT_DATA_IO_PU(168),		PORT_DATA_IO_PU(169),
-
-	PORT_DATA_IO_PU(170),		PORT_DATA_IO_PU(171),
-	PORT_DATA_IO_PD(172),		PORT_DATA_IO_PD(173),
-	PORT_DATA_IO_PD(174),		PORT_DATA_IO_PD(175),
-	PORT_DATA_IO_PU(176),		PORT_DATA_IO_PU_PD(177),
-	PORT_DATA_IO_PU(178),		PORT_DATA_IO_PD(179),
-
-	PORT_DATA_IO_PD(180),		PORT_DATA_IO_PU(181),
-	PORT_DATA_IO_PU(182),		PORT_DATA_IO(183),
-	PORT_DATA_IO_PD(184),		PORT_DATA_IO_PD(185),
-	PORT_DATA_IO_PD(186),		PORT_DATA_IO_PD(187),
-	PORT_DATA_IO_PD(188),		PORT_DATA_IO_PD(189),
-
-	PORT_DATA_IO_PD(190),		PORT_DATA_IO_PD(191),
-	PORT_DATA_IO_PD(192),		PORT_DATA_IO_PU_PD(193),
-	PORT_DATA_IO_PU_PD(194),	PORT_DATA_IO_PD(195),
-	PORT_DATA_IO_PU_PD(196),	PORT_DATA_IO_PD(197),
-	PORT_DATA_IO_PU_PD(198),	PORT_DATA_IO_PU_PD(199),
-
-	PORT_DATA_IO_PU_PD(200),	PORT_DATA_IO_PU(201),
-	PORT_DATA_IO_PU_PD(202),	PORT_DATA_IO(203),
-	PORT_DATA_IO_PU_PD(204),	PORT_DATA_IO_PU_PD(205),
-	PORT_DATA_IO_PU_PD(206),	PORT_DATA_IO_PU_PD(207),
-	PORT_DATA_IO_PU_PD(208),	PORT_DATA_IO_PD(209),
-
-	PORT_DATA_IO_PD(210),		PORT_DATA_IO_PD(211),
-
-	/* Port0 */
-	PINMUX_DATA(DBGMDT2_MARK,		PORT0_FN1),
-	PINMUX_DATA(FSIAISLD_PORT0_MARK,	PORT0_FN2,	MSEL5CR_3_0),
-	PINMUX_DATA(FSIAOSLD1_MARK,		PORT0_FN3),
-	PINMUX_DATA(LCD0_D22_PORT0_MARK,	PORT0_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(SCIFA7_RXD_MARK,		PORT0_FN6),
-	PINMUX_DATA(LCD1_D4_MARK,		PORT0_FN7),
-	PINMUX_DATA(IRQ5_PORT0_MARK,		PORT0_FN0,	MSEL1CR_5_0),
-
-	/* Port1 */
-	PINMUX_DATA(DBGMDT1_MARK,		PORT1_FN1),
-	PINMUX_DATA(FMSISLD_PORT1_MARK,		PORT1_FN2,	MSEL5CR_5_0),
-	PINMUX_DATA(FSIAOSLD2_MARK,		PORT1_FN3),
-	PINMUX_DATA(LCD0_D23_PORT1_MARK,	PORT1_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(SCIFA7_TXD_MARK,		PORT1_FN6),
-	PINMUX_DATA(LCD1_D3_MARK,		PORT1_FN7),
-	PINMUX_DATA(IRQ5_PORT1_MARK,		PORT1_FN0,	MSEL1CR_5_1),
-
-	/* Port2 */
-	PINMUX_DATA(DBGMDT0_MARK,		PORT2_FN1),
-	PINMUX_DATA(SCIFB_SCK_PORT2_MARK,	PORT2_FN2,	MSEL5CR_17_1),
-	PINMUX_DATA(LCD0_D21_PORT2_MARK,	PORT2_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(LCD1_D2_MARK,		PORT2_FN7),
-	PINMUX_DATA(IRQ0_PORT2_MARK,		PORT2_FN0,	MSEL1CR_0_1),
-
-	/* Port3 */
-	PINMUX_DATA(DBGMD21_MARK,		PORT3_FN1),
-	PINMUX_DATA(SCIFB_RXD_PORT3_MARK,	PORT3_FN2,	MSEL5CR_17_1),
-	PINMUX_DATA(LCD0_D20_PORT3_MARK,	PORT3_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(LCD1_D1_MARK,		PORT3_FN7),
-
-	/* Port4 */
-	PINMUX_DATA(DBGMD20_MARK,		PORT4_FN1),
-	PINMUX_DATA(SCIFB_TXD_PORT4_MARK,	PORT4_FN2,	MSEL5CR_17_1),
-	PINMUX_DATA(LCD0_D19_PORT4_MARK,	PORT4_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(LCD1_D0_MARK,		PORT4_FN7),
-
-	/* Port5 */
-	PINMUX_DATA(DBGMD11_MARK,		PORT5_FN1),
-	PINMUX_DATA(BBIF2_TXD2_PORT5_MARK,	PORT5_FN2,	MSEL5CR_0_0),
-	PINMUX_DATA(FSIAISLD_PORT5_MARK,	PORT5_FN4,	MSEL5CR_3_1),
-	PINMUX_DATA(RSPI_SSL0_A_MARK,		PORT5_FN6),
-	PINMUX_DATA(LCD1_VCPWC_MARK,		PORT5_FN7),
-
-	/* Port6 */
-	PINMUX_DATA(DBGMD10_MARK,		PORT6_FN1),
-	PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK,	PORT6_FN2,	MSEL5CR_0_0),
-	PINMUX_DATA(FMSISLD_PORT6_MARK,		PORT6_FN4,	MSEL5CR_5_1),
-	PINMUX_DATA(RSPI_SSL1_A_MARK,		PORT6_FN6),
-	PINMUX_DATA(LCD1_VEPWC_MARK,		PORT6_FN7),
-
-	/* Port7 */
-	PINMUX_DATA(FSIAOLR_MARK,		PORT7_FN1),
-
-	/* Port8 */
-	PINMUX_DATA(FSIAOBT_MARK,		PORT8_FN1),
-
-	/* Port9 */
-	PINMUX_DATA(FSIAOSLD_MARK,		PORT9_FN1),
-	PINMUX_DATA(FSIASPDIF_PORT9_MARK,	PORT9_FN2,	MSEL5CR_4_0),
-
-	/* Port10 */
-	PINMUX_DATA(FSIAOMC_MARK,		PORT10_FN1),
-	PINMUX_DATA(SCIFA5_RXD_PORT10_MARK,	PORT10_FN3,	MSEL5CR_14_0,	MSEL5CR_15_0),
-	PINMUX_DATA(IRQ3_PORT10_MARK,		PORT10_FN0,	MSEL1CR_3_0),
-
-	/* Port11 */
-	PINMUX_DATA(FSIACK_MARK,		PORT11_FN1),
-	PINMUX_DATA(FSIBCK_MARK,		PORT11_FN2),
-	PINMUX_DATA(IRQ2_PORT11_MARK,		PORT11_FN0,	MSEL1CR_2_0),
-
-	/* Port12 */
-	PINMUX_DATA(FSIAILR_MARK,		PORT12_FN1),
-	PINMUX_DATA(SCIFA4_RXD_PORT12_MARK,	PORT12_FN2,	MSEL5CR_12_0,	MSEL5CR_11_0),
-	PINMUX_DATA(LCD1_RS_MARK,		PORT12_FN6),
-	PINMUX_DATA(LCD1_DISP_MARK,		PORT12_FN7),
-	PINMUX_DATA(IRQ2_PORT12_MARK,		PORT12_FN0,	MSEL1CR_2_1),
-
-	/* Port13 */
-	PINMUX_DATA(FSIAIBT_MARK,		PORT13_FN1),
-	PINMUX_DATA(SCIFA4_TXD_PORT13_MARK,	PORT13_FN2,	MSEL5CR_12_0,	MSEL5CR_11_0),
-	PINMUX_DATA(LCD1_RD_MARK,		PORT13_FN7),
-	PINMUX_DATA(IRQ0_PORT13_MARK,		PORT13_FN0,	MSEL1CR_0_0),
-
-	/* Port14 */
-	PINMUX_DATA(FMSOILR_MARK,		PORT14_FN1),
-	PINMUX_DATA(FMSIILR_MARK,		PORT14_FN2),
-	PINMUX_DATA(VIO_CKO1_MARK,		PORT14_FN3),
-	PINMUX_DATA(LCD1_D23_MARK,		PORT14_FN7),
-	PINMUX_DATA(IRQ3_PORT14_MARK,		PORT14_FN0,	MSEL1CR_3_1),
-
-	/* Port15 */
-	PINMUX_DATA(FMSOIBT_MARK,		PORT15_FN1),
-	PINMUX_DATA(FMSIIBT_MARK,		PORT15_FN2),
-	PINMUX_DATA(VIO_CKO2_MARK,		PORT15_FN3),
-	PINMUX_DATA(LCD1_D22_MARK,		PORT15_FN7),
-	PINMUX_DATA(IRQ4_PORT15_MARK,		PORT15_FN0,	MSEL1CR_4_0),
-
-	/* Port16 */
-	PINMUX_DATA(FMSOOLR_MARK,		PORT16_FN1),
-	PINMUX_DATA(FMSIOLR_MARK,		PORT16_FN2),
-
-	/* Port17 */
-	PINMUX_DATA(FMSOOBT_MARK,		PORT17_FN1),
-	PINMUX_DATA(FMSIOBT_MARK,		PORT17_FN2),
-
-	/* Port18 */
-	PINMUX_DATA(FMSOSLD_MARK,		PORT18_FN1),
-	PINMUX_DATA(FSIASPDIF_PORT18_MARK,	PORT18_FN2,	MSEL5CR_4_1),
-
-	/* Port19 */
-	PINMUX_DATA(FMSICK_MARK,		PORT19_FN1),
-	PINMUX_DATA(CS5A_PORT19_MARK,		PORT19_FN7,	MSEL5CR_2_1),
-	PINMUX_DATA(IRQ10_MARK,			PORT19_FN0),
-
-	/* Port20 */
-	PINMUX_DATA(FMSOCK_MARK,		PORT20_FN1),
-	PINMUX_DATA(SCIFA5_TXD_PORT20_MARK,	PORT20_FN3,	MSEL5CR_15_0,	MSEL5CR_14_0),
-	PINMUX_DATA(IRQ1_MARK,			PORT20_FN0),
-
-	/* Port21 */
-	PINMUX_DATA(SCIFA1_CTS_MARK,		PORT21_FN1),
-	PINMUX_DATA(SCIFA4_SCK_PORT21_MARK,	PORT21_FN2,	MSEL5CR_10_0),
-	PINMUX_DATA(TPU0TO1_MARK,		PORT21_FN4),
-	PINMUX_DATA(VIO1_FIELD_MARK,		PORT21_FN5),
-	PINMUX_DATA(STP0_IPD5_MARK,		PORT21_FN6),
-	PINMUX_DATA(LCD1_D10_MARK,		PORT21_FN7),
-
-	/* Port22 */
-	PINMUX_DATA(SCIFA2_SCK_PORT22_MARK,	PORT22_FN1,	MSEL5CR_7_0),
-	PINMUX_DATA(SIM_D_PORT22_MARK,		PORT22_FN4,	MSEL5CR_21_0),
-	PINMUX_DATA(VIO0_D13_PORT22_MARK,	PORT22_FN7,	MSEL5CR_27_1),
-
-	/* Port23 */
-	PINMUX_DATA(SCIFA1_RTS_MARK,		PORT23_FN1),
-	PINMUX_DATA(SCIFA5_SCK_PORT23_MARK,	PORT23_FN3,	MSEL5CR_13_0),
-	PINMUX_DATA(TPU0TO0_MARK,		PORT23_FN4),
-	PINMUX_DATA(VIO_CKO_1_MARK,		PORT23_FN5),
-	PINMUX_DATA(STP0_IPD2_MARK,		PORT23_FN6),
-	PINMUX_DATA(LCD1_D7_MARK,		PORT23_FN7),
-
-	/* Port24 */
-	PINMUX_DATA(VIO0_D15_PORT24_MARK,	PORT24_FN1,	MSEL5CR_27_0),
-	PINMUX_DATA(VIO1_D7_MARK,		PORT24_FN5),
-	PINMUX_DATA(SCIFA6_SCK_MARK,		PORT24_FN6),
-	PINMUX_DATA(SDHI2_CD_PORT24_MARK,	PORT24_FN7,	MSEL5CR_19_0),
-
-	/* Port25 */
-	PINMUX_DATA(VIO0_D14_PORT25_MARK,	PORT25_FN1,	MSEL5CR_27_0),
-	PINMUX_DATA(VIO1_D6_MARK,		PORT25_FN5),
-	PINMUX_DATA(SCIFA6_RXD_MARK,		PORT25_FN6),
-	PINMUX_DATA(SDHI2_WP_PORT25_MARK,	PORT25_FN7,	MSEL5CR_19_0),
-
-	/* Port26 */
-	PINMUX_DATA(VIO0_D13_PORT26_MARK,	PORT26_FN1,	MSEL5CR_27_0),
-	PINMUX_DATA(VIO1_D5_MARK,		PORT26_FN5),
-	PINMUX_DATA(SCIFA6_TXD_MARK,		PORT26_FN6),
-
-	/* Port27 - Port39 Function */
-	PINMUX_DATA(VIO0_D7_MARK,		PORT27_FN1),
-	PINMUX_DATA(VIO0_D6_MARK,		PORT28_FN1),
-	PINMUX_DATA(VIO0_D5_MARK,		PORT29_FN1),
-	PINMUX_DATA(VIO0_D4_MARK,		PORT30_FN1),
-	PINMUX_DATA(VIO0_D3_MARK,		PORT31_FN1),
-	PINMUX_DATA(VIO0_D2_MARK,		PORT32_FN1),
-	PINMUX_DATA(VIO0_D1_MARK,		PORT33_FN1),
-	PINMUX_DATA(VIO0_D0_MARK,		PORT34_FN1),
-	PINMUX_DATA(VIO0_CLK_MARK,		PORT35_FN1),
-	PINMUX_DATA(VIO_CKO_MARK,		PORT36_FN1),
-	PINMUX_DATA(VIO0_HD_MARK,		PORT37_FN1),
-	PINMUX_DATA(VIO0_FIELD_MARK,		PORT38_FN1),
-	PINMUX_DATA(VIO0_VD_MARK,		PORT39_FN1),
-
-	/* Port38 IRQ */
-	PINMUX_DATA(IRQ25_MARK,			PORT38_FN0),
-
-	/* Port40 */
-	PINMUX_DATA(LCD0_D18_PORT40_MARK,	PORT40_FN4,	MSEL5CR_6_0),
-	PINMUX_DATA(RSPI_CK_A_MARK,		PORT40_FN6),
-	PINMUX_DATA(LCD1_LCLK_MARK,		PORT40_FN7),
-
-	/* Port41 */
-	PINMUX_DATA(LCD0_D17_MARK,		PORT41_FN1),
-	PINMUX_DATA(MSIOF2_SS1_MARK,		PORT41_FN2),
-	PINMUX_DATA(IRQ31_PORT41_MARK,		PORT41_FN0,	MSEL1CR_31_1),
-
-	/* Port42 */
-	PINMUX_DATA(LCD0_D16_MARK,		PORT42_FN1),
-	PINMUX_DATA(MSIOF2_MCK1_MARK,		PORT42_FN2),
-	PINMUX_DATA(IRQ12_PORT42_MARK,		PORT42_FN0,	MSEL1CR_12_1),
-
-	/* Port43 */
-	PINMUX_DATA(LCD0_D15_MARK,		PORT43_FN1),
-	PINMUX_DATA(MSIOF2_MCK0_MARK,		PORT43_FN2),
-	PINMUX_DATA(KEYIN0_PORT43_MARK,		PORT43_FN3,	MSEL4CR_18_0),
-	PINMUX_DATA(DV_D15_MARK,		PORT43_FN6),
-
-	/* Port44 */
-	PINMUX_DATA(LCD0_D14_MARK,		PORT44_FN1),
-	PINMUX_DATA(MSIOF2_RSYNC_MARK,		PORT44_FN2),
-	PINMUX_DATA(KEYIN1_PORT44_MARK,		PORT44_FN3,	MSEL4CR_18_0),
-	PINMUX_DATA(DV_D14_MARK,		PORT44_FN6),
-
-	/* Port45 */
-	PINMUX_DATA(LCD0_D13_MARK,		PORT45_FN1),
-	PINMUX_DATA(MSIOF2_RSCK_MARK,		PORT45_FN2),
-	PINMUX_DATA(KEYIN2_PORT45_MARK,		PORT45_FN3,	MSEL4CR_18_0),
-	PINMUX_DATA(DV_D13_MARK,		PORT45_FN6),
-
-	/* Port46 */
-	PINMUX_DATA(LCD0_D12_MARK,		PORT46_FN1),
-	PINMUX_DATA(KEYIN3_PORT46_MARK,		PORT46_FN3,	MSEL4CR_18_0),
-	PINMUX_DATA(DV_D12_MARK,		PORT46_FN6),
-
-	/* Port47 */
-	PINMUX_DATA(LCD0_D11_MARK,		PORT47_FN1),
-	PINMUX_DATA(KEYIN4_MARK,		PORT47_FN3),
-	PINMUX_DATA(DV_D11_MARK,		PORT47_FN6),
-
-	/* Port48 */
-	PINMUX_DATA(LCD0_D10_MARK,		PORT48_FN1),
-	PINMUX_DATA(KEYIN5_MARK,		PORT48_FN3),
-	PINMUX_DATA(DV_D10_MARK,		PORT48_FN6),
-
-	/* Port49 */
-	PINMUX_DATA(LCD0_D9_MARK,		PORT49_FN1),
-	PINMUX_DATA(KEYIN6_MARK,		PORT49_FN3),
-	PINMUX_DATA(DV_D9_MARK,			PORT49_FN6),
-	PINMUX_DATA(IRQ30_PORT49_MARK,		PORT49_FN0,	MSEL1CR_30_1),
-
-	/* Port50 */
-	PINMUX_DATA(LCD0_D8_MARK,		PORT50_FN1),
-	PINMUX_DATA(KEYIN7_MARK,		PORT50_FN3),
-	PINMUX_DATA(DV_D8_MARK,			PORT50_FN6),
-	PINMUX_DATA(IRQ29_PORT50_MARK,		PORT50_FN0,	MSEL1CR_29_1),
-
-	/* Port51 */
-	PINMUX_DATA(LCD0_D7_MARK,		PORT51_FN1),
-	PINMUX_DATA(KEYOUT0_MARK,		PORT51_FN3),
-	PINMUX_DATA(DV_D7_MARK,			PORT51_FN6),
-
-	/* Port52 */
-	PINMUX_DATA(LCD0_D6_MARK,		PORT52_FN1),
-	PINMUX_DATA(KEYOUT1_MARK,		PORT52_FN3),
-	PINMUX_DATA(DV_D6_MARK,			PORT52_FN6),
-
-	/* Port53 */
-	PINMUX_DATA(LCD0_D5_MARK,		PORT53_FN1),
-	PINMUX_DATA(KEYOUT2_MARK,		PORT53_FN3),
-	PINMUX_DATA(DV_D5_MARK,			PORT53_FN6),
-
-	/* Port54 */
-	PINMUX_DATA(LCD0_D4_MARK,		PORT54_FN1),
-	PINMUX_DATA(KEYOUT3_MARK,		PORT54_FN3),
-	PINMUX_DATA(DV_D4_MARK,			PORT54_FN6),
-
-	/* Port55 */
-	PINMUX_DATA(LCD0_D3_MARK,		PORT55_FN1),
-	PINMUX_DATA(KEYOUT4_MARK,		PORT55_FN3),
-	PINMUX_DATA(KEYIN3_PORT55_MARK,		PORT55_FN4,	MSEL4CR_18_1),
-	PINMUX_DATA(DV_D3_MARK,			PORT55_FN6),
-
-	/* Port56 */
-	PINMUX_DATA(LCD0_D2_MARK,		PORT56_FN1),
-	PINMUX_DATA(KEYOUT5_MARK,		PORT56_FN3),
-	PINMUX_DATA(KEYIN2_PORT56_MARK,		PORT56_FN4,	MSEL4CR_18_1),
-	PINMUX_DATA(DV_D2_MARK,			PORT56_FN6),
-	PINMUX_DATA(IRQ28_PORT56_MARK,		PORT56_FN0,	MSEL1CR_28_1),
-
-	/* Port57 */
-	PINMUX_DATA(LCD0_D1_MARK,		PORT57_FN1),
-	PINMUX_DATA(KEYOUT6_MARK,		PORT57_FN3),
-	PINMUX_DATA(KEYIN1_PORT57_MARK,		PORT57_FN4,	MSEL4CR_18_1),
-	PINMUX_DATA(DV_D1_MARK,			PORT57_FN6),
-	PINMUX_DATA(IRQ27_PORT57_MARK,		PORT57_FN0,	MSEL1CR_27_1),
-
-	/* Port58 */
-	PINMUX_DATA(LCD0_D0_MARK,		PORT58_FN1),
-	PINMUX_DATA(KEYOUT7_MARK,		PORT58_FN3),
-	PINMUX_DATA(KEYIN0_PORT58_MARK,		PORT58_FN4,	MSEL4CR_18_1),
-	PINMUX_DATA(DV_D0_MARK,			PORT58_FN6),
-	PINMUX_DATA(IRQ26_PORT58_MARK,		PORT58_FN0,	MSEL1CR_26_1),
-
-	/* Port59 */
-	PINMUX_DATA(LCD0_VCPWC_MARK,		PORT59_FN1),
-	PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK,	PORT59_FN2,	MSEL5CR_0_0),
-	PINMUX_DATA(RSPI_MOSI_A_MARK,		PORT59_FN6),
-
-	/* Port60 */
-	PINMUX_DATA(LCD0_VEPWC_MARK,		PORT60_FN1),
-	PINMUX_DATA(BBIF2_RXD2_PORT60_MARK,	PORT60_FN2,	MSEL5CR_0_0),
-	PINMUX_DATA(RSPI_MISO_A_MARK,		PORT60_FN6),
-
-	/* Port61 */
-	PINMUX_DATA(LCD0_DON_MARK,		PORT61_FN1),
-	PINMUX_DATA(MSIOF2_TXD_MARK,		PORT61_FN2),
-
-	/* Port62 */
-	PINMUX_DATA(LCD0_DCK_MARK,		PORT62_FN1),
-	PINMUX_DATA(LCD0_WR_MARK,		PORT62_FN4),
-	PINMUX_DATA(DV_CLK_MARK,		PORT62_FN6),
-	PINMUX_DATA(IRQ15_PORT62_MARK,		PORT62_FN0,	MSEL1CR_15_1),
-
-	/* Port63 */
-	PINMUX_DATA(LCD0_VSYN_MARK,		PORT63_FN1),
-	PINMUX_DATA(DV_VSYNC_MARK,		PORT63_FN6),
-	PINMUX_DATA(IRQ14_PORT63_MARK,		PORT63_FN0,	MSEL1CR_14_1),
-
-	/* Port64 */
-	PINMUX_DATA(LCD0_HSYN_MARK,		PORT64_FN1),
-	PINMUX_DATA(LCD0_CS_MARK,		PORT64_FN4),
-	PINMUX_DATA(DV_HSYNC_MARK,		PORT64_FN6),
-	PINMUX_DATA(IRQ13_PORT64_MARK,		PORT64_FN0,	MSEL1CR_13_1),
-
-	/* Port65 */