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authorWolfram Sang <wsa@sang-engineering.com>2014-02-28 10:32:55 +0100
committerSimon Horman <horms+renesas@verge.net.au>2014-03-06 13:22:02 +0900
commitd93023f81d2c79595e64e4f516f03af4e4c73c13 (patch)
treeac4050e829e0ec09ceaf251b2c70de55463e2c65 /arch/arm/mach-shmobile
parent9ced1d47719b5f32e4231338dd362c136518ed08 (diff)
ARM: shmobile: r7s72100: fix bus clock calculation
The picture in the datasheet is a little misleading, yet the divider of the bus_clk is 1/3 and not 2/3. Signed-off-by: Wolfram Sang <wsa@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/mach-shmobile')
-rw-r--r--arch/arm/mach-shmobile/clock-r7s72100.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index f17a5db0022..bee0073c9b6 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -70,7 +70,7 @@ static struct clk pll_clk = {
static unsigned long bus_recalc(struct clk *clk)
{
- return clk->parent->rate * 2 / 3;
+ return clk->parent->rate / 3;
}
static struct sh_clk_ops bus_clk_ops = {