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authorLinus Torvalds <torvalds@linux-foundation.org>2011-07-29 23:35:05 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2011-07-29 23:35:05 -0700
commitf85f19de90a9997583bb26e6f1f9297a4e152c18 (patch)
tree2dfe61dab6c39ca202f114cb68c68978da1624e3 /arch/arm/mach-sa1100
parentb993fdbc7fe26f96b59003a3552c418a71aa0a9f (diff)
parent7b87c9df5602efd6c7edeb291bbd104d49a6babf (diff)
Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: PCI: remove printks about disabled bridge windows PCI: fold pci_calc_resource_flags() into decode_bar() PCI: treat mem BAR type "11" (reserved) as 32-bit, not 64-bit, BAR PCI: correct pcie_set_readrq write size PCI: pciehp: change wait time for valid configuration access x86/PCI: Preserve existing pci=bfsort whitelist for Dell systems PCI: ARI is a PCIe v2 feature x86/PCI: quirks: Use pci_dev->revision PCI: Make the struct pci_dev * argument of pci_fixup_irqs const. PCI hotplug: cpqphp: use pci_dev->vendor PCI hotplug: cpqphp: use pci_dev->subsystem_{vendor|device} x86/PCI: config space accessor functions should not ignore the segment argument PCI: Assign values to 'pci_obff_signal_type' enumeration constants x86/PCI: reduce severity of host bridge window conflict warnings PCI: enumerate the PCI device only removed out PCI hieratchy of OS when re-scanning PCI PCI: PCIe AER: add aer_recover_queue x86/PCI: select direct access mode for mmconfig option PCI hotplug: Rename is_ejectable which also exists in dock.c
Diffstat (limited to 'arch/arm/mach-sa1100')
-rw-r--r--arch/arm/mach-sa1100/pci-nanoengine.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index 5fc074fe3ee..964c6c3cd7a 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -122,7 +122,8 @@ static struct pci_ops pci_nano_ops = {
.write = nanoengine_write_config,
};
-static int __init pci_nanoengine_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
+ u8 pin)
{
return NANOENGINE_IRQ_GPIO_PCI;
}