diff options
| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-08-05 16:14:15 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-08-07 09:55:48 +0100 |
| commit | a09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch) | |
| tree | 69689f467179891b498bd7423fcf61925173db31 /arch/arm/mach-sa1100 | |
| parent | a1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff) | |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-sa1100')
61 files changed, 5293 insertions, 56 deletions
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index d219845b10b..55e64477a87 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -20,7 +20,7 @@ #include <linux/delay.h> #include <linux/mm.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/irq.h> #include <asm/setup.h> @@ -34,8 +34,8 @@ #include <asm/mach/irda.h> #include <asm/mach/map.h> #include <asm/mach/serial_sa1100.h> -#include <asm/arch/assabet.h> -#include <asm/arch/mcp.h> +#include <mach/assabet.h> +#include <mach/mcp.h> #include "generic.h" diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c index d087c3bf3fe..3efefbdd252 100644 --- a/arch/arm/mach-sa1100/badge4.c +++ b/arch/arm/mach-sa1100/badge4.c @@ -23,10 +23,10 @@ #include <linux/mtd/partitions.h> #include <linux/errno.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/setup.h> -#include <asm/arch/irqs.h> +#include <mach/irqs.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> @@ -34,7 +34,7 @@ #include <asm/hardware/sa1111.h> #include <asm/mach/serial_sa1100.h> -#include <asm/arch/badge4.h> +#include <mach/badge4.h> #include "generic.h" diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c index cfb65eb9f30..fd3ad9cfc91 100644 --- a/arch/arm/mach-sa1100/cerf.c +++ b/arch/arm/mach-sa1100/cerf.c @@ -19,7 +19,7 @@ #include <linux/mtd/partitions.h> #include <asm/irq.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -28,8 +28,8 @@ #include <asm/mach/map.h> #include <asm/mach/serial_sa1100.h> -#include <asm/arch/cerf.h> -#include <asm/arch/mcp.h> +#include <mach/cerf.h> +#include <mach/mcp.h> #include "generic.h" static struct resource cerfuart2_resources[] = { diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index dbd1aaaa09a..43c30f84abf 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -11,7 +11,7 @@ #include <linux/spinlock.h> #include <linux/mutex.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> /* * Very simple clock implementation - we only have one clock to diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 40893638be7..fe289997cfa 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -26,11 +26,11 @@ #include <linux/mtd/partitions.h> #include <linux/timer.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/irq.h> #include <asm/setup.h> -#include <asm/arch/collie.h> +#include <mach/collie.h> #include <asm/mach/arch.h> #include <asm/mach/flash.h> @@ -40,7 +40,7 @@ #include <asm/hardware/scoop.h> #include <asm/mach/sharpsl_param.h> #include <asm/hardware/locomo.h> -#include <asm/arch/mcp.h> +#include <mach/mcp.h> #include "generic.h" diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c index daa9d57c00f..b1161fc8060 100644 --- a/arch/arm/mach-sa1100/collie_pm.c +++ b/arch/arm/mach-sa1100/collie_pm.c @@ -24,10 +24,10 @@ #include <linux/platform_device.h> #include <asm/irq.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include <asm/hardware/scoop.h> #include <asm/dma.h> -#include <asm/arch/collie.h> +#include <mach/collie.h> #include <asm/mach/sharpsl_param.h> #include <asm/hardware/sharpsl_pm.h> diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c index 61df76f8526..da3a898a6d6 100644 --- a/arch/arm/mach-sa1100/cpu-sa1100.c +++ b/arch/arm/mach-sa1100/cpu-sa1100.c @@ -88,7 +88,7 @@ #include <linux/init.h> #include <linux/cpufreq.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include "generic.h" diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c index a471f9f6273..39d38c80173 100644 --- a/arch/arm/mach-sa1100/cpu-sa1110.c +++ b/arch/arm/mach-sa1100/cpu-sa1110.c @@ -26,7 +26,7 @@ #include <linux/delay.h> #include <linux/init.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/io.h> #include <asm/system.h> diff --git a/arch/arm/mach-sa1100/dma.c b/arch/arm/mach-sa1100/dma.c index 65d96eec9e6..f990a3e8584 100644 --- a/arch/arm/mach-sa1100/dma.c +++ b/arch/arm/mach-sa1100/dma.c @@ -18,7 +18,7 @@ #include <asm/system.h> #include <asm/irq.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include <asm/dma.h> @@ -76,7 +76,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) * address of the hardware registers for that channel as the channel * identifier. This identifier is written to the location pointed by * @dma_regs. The list of possible values for @device are listed into - * linux/include/asm-arm/arch-sa1100/dma.h as a dma_device_t enum. + * arch/arm/mach-sa1100/include/mach/dma.h as a dma_device_t enum. * * Note that reading from a port and writing to the same port are * actually considered as two different streams requiring separate diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c index e616130ae52..5a08fe20a31 100644 --- a/arch/arm/mach-sa1100/generic.c +++ b/arch/arm/mach-sa1100/generic.c @@ -21,7 +21,7 @@ #include <asm/div64.h> #include <asm/cnt32_to_63.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include <asm/system.h> #include <asm/pgtable.h> #include <asm/mach/map.h> diff --git a/arch/arm/mach-sa1100/gpio.c b/arch/arm/mach-sa1100/gpio.c index 184b04c0072..0d3829a8c2c 100644 --- a/arch/arm/mach-sa1100/gpio.c +++ b/arch/arm/mach-sa1100/gpio.c @@ -12,7 +12,7 @@ #include <linux/module.h> #include <asm/gpio.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include "generic.h" static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset) diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c index 8c560ae0869..af25a78d705 100644 --- a/arch/arm/mach-sa1100/h3600.c +++ b/arch/arm/mach-sa1100/h3600.c @@ -30,7 +30,7 @@ #include <linux/serial_core.h> #include <asm/irq.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/setup.h> @@ -41,14 +41,14 @@ #include <asm/mach/map.h> #include <asm/mach/serial_sa1100.h> -#include <asm/arch/h3600.h> +#include <mach/h3600.h> #if defined (CONFIG_SA1100_H3600) || defined (CONFIG_SA1100_H3100) -#include <asm/arch/h3600_gpio.h> +#include <mach/h3600_gpio.h> #endif #ifdef CONFIG_SA1100_H3800 -#include <asm/arch/h3600_asic.h> +#include <mach/h3600_asic.h> #endif #include "generic.h" @@ -681,7 +681,7 @@ static struct ipaq_model_ops h3800_model_ops __initdata = { #define MAX_ASIC_ISR_LOOPS 20 -/* The order of these is important - see #include <asm/arch/irqs.h> */ +/* The order of these is important - see #include <mach/irqs.h> */ static u32 kpio_irq_mask[] = { KPIO_KEY_ALL, KPIO_SPI_INT, diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c index 270feb0fa4a..e7056c0b562 100644 --- a/arch/arm/mach-sa1100/hackkit.c +++ b/arch/arm/mach-sa1100/hackkit.c @@ -22,7 +22,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> -#include <asm/arch/hardware.h> +#include <mach/hardware.h> #include <asm/mach-types.h> #include <asm/setup.h> #include <asm/page.h> diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h new file mode 100644 index 00000000000..62aaf04a390 --- /dev/null +++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h @@ -0,0 +1,2072 @@ +/* + * FILE SA-1100.h + * + * Version 1.2 + * Author Copyright (c) Marc A. Viredaz, 1998 + * DEC Western Research Laboratory, Palo Alto, CA + * Date January 1998 (April 1997) + * System StrongARM SA-1100 + * Language C or ARM Assembly + * Purpose Definition of constants related to the StrongARM + * SA-1100 microprocessor (Advanced RISC Machine (ARM) + * architecture version 4). This file is based on the + * StrongARM SA-1100 data sheet version 2.2. + * + */ + + +/* Be sure that virtual mapping is defined right */ +#ifndef __ASM_ARCH_HARDWARE_H +#error You must include hardware.h not SA-1100.h +#endif + +#include "bitfield.h" + +/* + * SA1100 CS line to physical address + */ + +#define SA1100_CS0_PHYS 0x00000000 +#define SA1100_CS1_PHYS 0x08000000 +#define SA1100_CS2_PHYS 0x10000000 +#define SA1100_CS3_PHYS 0x18000000 +#define SA1100_CS4_PHYS 0x40000000 +#define SA1100_CS5_PHYS 0x48000000 + +/* + * Personal Computer Memory Card International Association (PCMCIA) sockets + */ + +#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ +#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ +#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ +#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ +#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ + +#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ +#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ +#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ +#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ + +#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ +#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ +#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ +#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ + +#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ + (0x20000000 + (Nb)*PCMCIASp) +#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ +#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ + (_PCMCIA (Nb) + 2*PCMCIAPrtSp) +#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ + (_PCMCIA (Nb) + 3*PCMCIAPrtSp) + +#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ +#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ +#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ +#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ + +#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ +#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ +#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ +#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ + + +/* + * Universal Serial Bus (USB) Device Controller (UDC) control registers + * + * Registers + * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control Register (read/write). + * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Address Register (read/write). + * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Output Maximum Packet size register + * (read/write). + * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Input Maximum Packet size register + * (read/write). + * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 0 + * (read/write). + * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 1 + * (output, read/write). + * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Control/Status register end-point 2 + * (input, read/write). + * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data register end-point 0 + * (read/write). + * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Write Count register end-point 0 + * (read). + * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Data Register (read/write). + * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device + * Controller (UDC) Status Register (read/write). + */ + +#define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */ +#define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */ +#define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */ +#define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */ +#define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */ +#define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */ +#define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */ +#define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */ +#define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */ +#define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */ +#define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */ + +#define UDCCR_UDD 0x00000001 /* UDC Disable */ +#define UDCCR_UDA 0x00000002 /* UDC Active (read) */ +#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */ +#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */ + /* (disable) */ +#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */ + /* (disable) */ +#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */ + /* (disable) */ +#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */ + /* (disable) */ +#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */ +#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */ + +#define UDCAR_ADD Fld (7, 0) /* function ADDress */ + +#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */ + /* [byte] */ +#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \ + /* [1..256 byte] */ \ + (((Size) - 1) << FShft (UDCOMP_OUTMAXP)) + +#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */ + /* [byte] */ +#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \ + /* [1..256 byte] */ \ + (((Size) - 1) << FShft (UDCIMP_INMAXP)) + +#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */ +#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */ +#define UDCCS0_SST 0x00000004 /* Sent STall */ +#define UDCCS0_FST 0x00000008 /* Force STall */ +#define UDCCS0_DE 0x00000010 /* Data End */ +#define UDCCS0_SE 0x00000020 /* Setup End (read) */ +#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */ + /* (write) */ +#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */ + +#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */ + /* Service request (read) */ +#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */ +#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */ +#define UDCCS1_SST 0x00000008 /* Sent STall */ +#define UDCCS1_FST 0x00000010 /* Force STall */ +#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */ + +#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */ + /* Service request (read) */ +#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */ +#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */ +#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */ +#define UDCCS2_SST 0x00000010 /* Sent STall */ +#define UDCCS2_FST 0x00000020 /* Force STall */ + +#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ + +#define UDCWC_WC Fld (4, 0) /* Write Count */ + +#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */ + +#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */ +#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */ +#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */ +#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */ +#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */ +#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */ + + +/* + * Universal Asynchronous Receiver/Transmitter (UART) control registers + * + * Registers + * Ser1UTCR0 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 0 + * (read/write). + * Ser1UTCR1 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 1 + * (read/write). + * Ser1UTCR2 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 2 + * (read/write). + * Ser1UTCR3 Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Control Register 3 + * (read/write). + * Ser1UTDR Serial port 1 Universal Asynchronous + * Receiver/Transmitter (UART) Data Register + * (read/write). |