diff options
author | Heiko Stuebner <heiko@sntech.de> | 2013-02-12 09:59:24 -0800 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-03-05 20:20:38 +0900 |
commit | 2286cf467e460eabfd0a188c5c5fb46955dcf024 (patch) | |
tree | 395af26fd2846ded9c75538124d6c163cd715a68 /arch/arm/mach-s3c24xx/irq.c | |
parent | ce6c164bf0ea44fad7969e1f1027d4f6cfb30360 (diff) |
ARM: S3C24XX: move s3c2440 irqs to common irq code
Will be integrated in the following patch.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c24xx/irq.c')
-rw-r--r-- | arch/arm/mach-s3c24xx/irq.c | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c index 2c59b2d99a8..1804e23baad 100644 --- a/arch/arm/mach-s3c24xx/irq.c +++ b/arch/arm/mach-s3c24xx/irq.c @@ -784,6 +784,94 @@ static struct irq_chip s3c_irq_cam = { }; #ifdef CONFIG_CPU_S3C2440 +/* WDT/AC97 */ + +static void s3c_irq_demux_wdtac97(unsigned int irq, + struct irq_desc *desc) +{ + unsigned int subsrc, submsk; + + /* read the current pending interrupts, and the mask + * for what it is available */ + + subsrc = __raw_readl(S3C2410_SUBSRCPND); + submsk = __raw_readl(S3C2410_INTSUBMSK); + + subsrc &= ~submsk; + subsrc >>= 13; + subsrc &= 3; + + if (subsrc != 0) { + if (subsrc & 1) { + generic_handle_irq(IRQ_S3C2440_WDT); + } + if (subsrc & 2) { + generic_handle_irq(IRQ_S3C2440_AC97); + } + } +} + + +#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0)) + +static void +s3c_irq_wdtac97_mask(struct irq_data *data) +{ + s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13); +} + +static void +s3c_irq_wdtac97_unmask(struct irq_data *data) +{ + s3c_irqsub_unmask(data->irq, INTMSK_WDT); +} + +static void +s3c_irq_wdtac97_ack(struct irq_data *data) +{ + s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13); +} + +static struct irq_chip s3c_irq_wdtac97 = { + .irq_mask = s3c_irq_wdtac97_mask, + .irq_unmask = s3c_irq_wdtac97_unmask, + .irq_ack = s3c_irq_wdtac97_ack, +}; + +static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif) +{ + unsigned int irqno; + + printk("S3C2440: IRQ Support\n"); + + /* add new chained handler for wdt, ac7 */ + + irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip, + handle_level_irq); + irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97); + + for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) { + irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97, + handle_level_irq); + set_irq_flags(irqno, IRQF_VALID); + } + + return 0; +} + +static struct subsys_interface s3c2440_irq_interface = { + .name = "s3c2440_irq", + .subsys = &s3c2440_subsys, + .add_dev = s3c2440_irq_add, +}; + +static int s3c2440_irq_init(void) +{ + return subsys_interface_register(&s3c2440_irq_interface); +} + +arch_initcall(s3c2440_irq_init); + void __init s3c2440_init_irq(void) { unsigned int irqno; |