diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-12-12 11:40:13 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-12-12 11:40:13 -0800 |
commit | 9c3936cb694ffd559c80dc3eb75b61f769a39259 (patch) | |
tree | cc034c09e359e43b4ff01efabc7ce47602d80acf /arch/arm/mach-omap2/omap-smp.c | |
parent | 5de76b18d1a7193c49c1a4ee72261421a17de57c (diff) | |
parent | 5ccf197859d6f6bcf56e85657019503b2d95767a (diff) |
Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (75 commits)
omap3: Fix OMAP35XX_REV macros
omap: serial: fix non-empty uart fifo read abort
omap3: Zoom2/3: Update hsmmc board config params
omap3 : Enable TWL4030 Keypad for Zoom2 and Zoom3 boards
omap3: id code detection 3525 vs 3515
omap3: rx51: Use wl1251 in SPI mode 3
omap3: zoom2/3: make MMC slot work again
omap1: htcherald: Update defconfig to include mux support
omap1: LCD_DMA: Use some define rather than a hexadecimal
omap: header: remove unused data-type
omap: arch/arm/plat-omap/devices.c - sort alphabetically
omap: Correcting GPMC_CONFIG1_DEVICETYPE_NAND
OMAP3: serial - allow platforms specify which UARTs to initialize
omap3: cm-t35: add mux initialization
OMAP4: Sync up omap4430 defconfig
OMAP4: Remove the secondary wait loop
OMAP4: AuxCoreBoot registers only accessible in secure mode
OMAP4: Fix SRAM base and size
OMAP4: Fix cpu detection
omap3: pandora: board file updates for .33
...
Diffstat (limited to 'arch/arm/mach-omap2/omap-smp.c')
-rw-r--r-- | arch/arm/mach-omap2/omap-smp.c | 31 |
1 files changed, 8 insertions, 23 deletions
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 4890bcf4dad..38153e5fbca 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -17,19 +17,15 @@ */ #include <linux/init.h> #include <linux/device.h> -#include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> +#include <asm/cacheflush.h> #include <asm/localtimer.h> #include <asm/smp_scu.h> #include <mach/hardware.h> #include <plat/common.h> -/* Registers used for communicating startup information */ -static void __iomem *omap4_auxcoreboot_reg0; -static void __iomem *omap4_auxcoreboot_reg1; - /* SCU base address */ static void __iomem *scu_base; @@ -65,8 +61,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu) int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { - unsigned long timeout; - /* * Set synchronisation state between this boot processor * and the secondary one @@ -74,18 +68,15 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) spin_lock(&boot_lock); /* - * Update the AuxCoreBoot1 with boot state for secondary core. + * Update the AuxCoreBoot0 with boot state for secondary core. * omap_secondary_startup() routine will hold the secondary core till * the AuxCoreBoot1 register is updated with cpu state * A barrier is added to ensure that write buffer is drained */ - __raw_writel(cpu, omap4_auxcoreboot_reg1); + omap_modify_auxcoreboot0(0x200, 0x0); + flush_cache_all(); smp_wmb(); - timeout = jiffies + (1 * HZ); - while (time_before(jiffies, timeout)) - ; - /* * Now the secondary core is starting up let it run its * calibrations, then wait for it to finish @@ -99,17 +90,18 @@ static void __init wakeup_secondary(void) { /* * Write the address of secondary startup routine into the - * AuxCoreBoot0 where ROM code will jump and start executing + * AuxCoreBoot1 where ROM code will jump and start executing * on secondary core once out of WFE * A barrier is added to ensure that write buffer is drained */ - __raw_writel(virt_to_phys(omap_secondary_startup), \ - omap4_auxcoreboot_reg0); + omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); smp_wmb(); /* * Send a 'sev' to wake the secondary core from WFE. + * Drain the outstanding writes to memory */ + dsb(); set_event(); mb(); } @@ -136,7 +128,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) { unsigned int ncores = get_core_count(); unsigned int cpu = smp_processor_id(); - void __iomem *omap4_wkupgen_base; int i; /* sanity check */ @@ -168,12 +159,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus) for (i = 0; i < max_cpus; i++) set_cpu_present(i, true); - /* Never released */ - omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K); - BUG_ON(!omap4_wkupgen_base); - omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800; - omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804; - if (max_cpus > 1) { /* * Enable the local timer or broadcast device for the |