diff options
author | Paul Walmsley <paul@pwsan.com> | 2010-02-22 22:09:36 -0700 |
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committer | Paul Walmsley <paul@pwsan.com> | 2010-02-24 17:45:15 -0700 |
commit | 4d30e82c26b7212021b9a5ab57760d9b8a3075fe (patch) | |
tree | b824e735401ccf62eb762db68d06c4bd3231fab5 /arch/arm/mach-omap2/clock2xxx.c | |
parent | ad9561609c41f704fd82facd37127e957bcaea94 (diff) |
OMAP2/3 clock: combine OMAP2 & 3 boot-time MPU rate change code
The OMAP2 and OMAP3 boot-time MPU rate change code is almost
identical. Merge them into mach-omap2/clock.c, and add kerneldoc
documentation.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock2xxx.c')
-rw-r--r-- | arch/arm/mach-omap2/clock2xxx.c | 34 |
1 files changed, 9 insertions, 25 deletions
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index 7a2f5ad07ba..80bb0f0e92e 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c @@ -50,40 +50,24 @@ void omap2xxx_clk_prepare_for_reboot(void) } /* - * Switch the MPU rate if specified on cmdline. - * We cannot do this early until cmdline is parsed. + * Switch the MPU rate if specified on cmdline. We cannot do this + * early until cmdline is parsed. XXX This should be removed from the + * clock code and handled by the OPP layer code in the near future. */ static int __init omap2xxx_clk_arch_init(void) { - struct clk *virt_prcm_set, *sys_ck, *dpll_ck, *mpu_ck; - unsigned long sys_ck_rate; + int ret; if (!cpu_is_omap24xx()) return 0; - if (!mpurate) - return -EINVAL; + ret = omap2_clk_switch_mpurate_at_boot("virt_prcm_set"); + if (!ret) + omap2_clk_print_new_rates("sys_ck", "dpll_ck", "mpu_ck"); - virt_prcm_set = clk_get(NULL, "virt_prcm_set"); - sys_ck = clk_get(NULL, "sys_ck"); - dpll_ck = clk_get(NULL, "dpll_ck"); - mpu_ck = clk_get(NULL, "mpu_ck"); - - if (clk_set_rate(virt_prcm_set, mpurate)) - pr_err("Could not find matching MPU rate\n"); - - recalculate_root_clocks(); - - sys_ck_rate = clk_get_rate(sys_ck); - - pr_info("Switched to new clocking rate (Crystal/DPLL/MPU): " - "%ld.%01ld/%ld/%ld MHz\n", - (sys_ck_rate / 1000000), (sys_ck_rate / 100000) % 10, - (clk_get_rate(dpll_ck) / 1000000), - (clk_get_rate(mpu_ck) / 1000000)); - - return 0; + return ret; } + arch_initcall(omap2xxx_clk_arch_init); |