diff options
| author | Steve Muckle <smuckle@codeaurora.org> | 2010-02-11 11:50:40 -0800 |
|---|---|---|
| committer | Daniel Walker <dwalker@codeaurora.org> | 2010-10-08 15:12:40 -0700 |
| commit | 9161d303af547653c66dab4e235b6fd0c3ac6148 (patch) | |
| tree | e6440360226316622b6a65231ea6229d44b26cb5 /arch/arm/mach-msm | |
| parent | f880c5649ec7a831a45cd254e9ecf9bd25b17dba (diff) | |
msm: 8x60: gic initialization fixup for RUMI
On RUMI platform STIs are not enabled by default, contrary to the
GIC spec. The bits for STIs in the enable/enable clear registers
are also RW instead of RO. STIs need to be enabled at initialization
time.
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm')
| -rw-r--r-- | arch/arm/mach-msm/board-msm8x60.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index d30ead14500..e7feb99b5cf 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c @@ -19,6 +19,7 @@ #include <linux/kernel.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/irq.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -41,9 +42,28 @@ static void __init msm8x60_map_io(void) static void __init msm8x60_init_irq(void) { + unsigned int i; + gic_dist_init(0, MSM_QGIC_DIST_BASE, 1); gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE; gic_cpu_init(0, MSM_QGIC_CPU_BASE); + + /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ + writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); + + /* RUMI does not adhere to GIC spec by enabling STIs by default. + * Enable/clear is supposed to be RO for STIs, but is RW on RUMI. + */ + writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); + + /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet + * as they are configured as level, which does not play nice with + * handle_percpu_irq. + */ + for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { + if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) + set_irq_handler(i, handle_percpu_irq); + } } static void __init msm8x60_init(void) |