Merge ../linux-2.6

8 files changed, 1302 insertions, 0 deletions

diff --git a/arch/arm/mach-ixp23xx/Kconfig b/arch/arm/mach-ixp23xx/Kconfig
new file mode 100644
index 00000000000..982670ec386
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Kconfig
@@ -0,0 +1,25 @@
+if ARCH_IXP23XX
+
+config ARCH_SUPPORTS_BIG_ENDIAN
+	bool
+	default y
+
+menu "Intel IXP23xx Implementation Options"
+
+comment "IXP23xx Platforms"
+
+config MACH_ESPRESSO
+	bool "Support IP Fabrics Double Espresso platform"
+	help
+
+config MACH_IXDP2351
+	bool "Support Intel IXDP2351 platform"
+	help
+
+config MACH_ROADRUNNER
+	bool "Support ADI RoadRunner platform"
+	help
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-ixp23xx/Makefile b/arch/arm/mach-ixp23xx/Makefile
new file mode 100644
index 00000000000..288b371b6d0
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Makefile
@@ -0,0 +1,11 @@
+#
+# Makefile for the linux kernel.
+#
+obj-y			:= core.o pci.o
+obj-m			:=
+obj-n			:=
+obj-			:=
+
+obj-$(CONFIG_MACH_ESPRESSO)	+= espresso.o
+obj-$(CONFIG_MACH_IXDP2351)	+= ixdp2351.o
+obj-$(CONFIG_MACH_ROADRUNNER)	+= roadrunner.o
diff --git a/arch/arm/mach-ixp23xx/Makefile.boot b/arch/arm/mach-ixp23xx/Makefile.boot
new file mode 100644
index 00000000000..d5561ad15ba
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Makefile.boot
@@ -0,0 +1,2 @@
+   zreladdr-y	:= 0x00008000
+params_phys-y	:= 0x00000100
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
new file mode 100644
index 00000000000..092ee12ced4
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -0,0 +1,431 @@
+/*
+ * arch/arm/mach-ixp23xx/core.c
+ *
+ * Core routines for IXP23xx chips
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2005 (c) MontaVista Software, Inc.
+ *
+ * Based on 2.4 code Copyright 2004 (c) Intel Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/bitops.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_core.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/time.h>
+#include <linux/timex.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/tlbflush.h>
+#include <asm/pgtable.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+
+
+/*************************************************************************
+ * Chip specific mappings shared by all IXP23xx systems
+ *************************************************************************/
+static struct map_desc ixp23xx_io_desc[] __initdata = {
+	{ /* XSI-CPP CSRs */
+	 	.virtual	= IXP23XX_XSI2CPP_CSR_VIRT,
+	 	.pfn		= __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
+	 	.length		= IXP23XX_XSI2CPP_CSR_SIZE,
+		.type		= MT_DEVICE,
+	}, { /* Expansion Bus Config */
+	 	.virtual	= IXP23XX_EXP_CFG_VIRT,
+	 	.pfn		= __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
+	 	.length		= IXP23XX_EXP_CFG_SIZE,
+		.type		= MT_DEVICE,
+	}, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
+	 	.virtual	= IXP23XX_PERIPHERAL_VIRT,
+	 	.pfn		= __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
+	 	.length		= IXP23XX_PERIPHERAL_SIZE,
+		.type		= MT_DEVICE,
+	}, { /* CAP CSRs */
+	 	.virtual	= IXP23XX_CAP_CSR_VIRT,
+	 	.pfn		= __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
+	 	.length		= IXP23XX_CAP_CSR_SIZE,
+		.type		= MT_DEVICE,
+	}, { /* MSF CSRs */
+	 	.virtual	= IXP23XX_MSF_CSR_VIRT,
+	 	.pfn		= __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
+	 	.length		= IXP23XX_MSF_CSR_SIZE,
+		.type		= MT_DEVICE,
+	}, { /* PCI I/O Space */
+	 	.virtual	= IXP23XX_PCI_IO_VIRT,
+	 	.pfn		= __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
+	 	.length		= IXP23XX_PCI_IO_SIZE,
+		.type		= MT_DEVICE,
+	}, { /* PCI Config Space */
+	 	.virtual	= IXP23XX_PCI_CFG_VIRT,
+	 	.pfn		= __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
+	 	.length		= IXP23XX_PCI_CFG_SIZE,
+		.type		= MT_DEVICE,
+	}, { /* PCI local CFG CSRs */
+	 	.virtual	= IXP23XX_PCI_CREG_VIRT,
+	 	.pfn		= __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
+	 	.length		= IXP23XX_PCI_CREG_SIZE,
+		.type		= MT_DEVICE,
+	}, { /* PCI MEM Space */
+	 	.virtual	= IXP23XX_PCI_MEM_VIRT,
+	 	.pfn		= __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
+	 	.length		= IXP23XX_PCI_MEM_SIZE,
+		.type		= MT_DEVICE,
+	}
+};
+
+void __init ixp23xx_map_io(void)
+{
+	iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
+}
+
+
+/***************************************************************************
+ * IXP23xx Interrupt Handling
+ ***************************************************************************/
+enum ixp23xx_irq_type {
+	IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
+};
+
+static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
+
+static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
+{
+	int line = irq - IRQ_IXP23XX_GPIO6 + 6;
+	u32 int_style;
+	enum ixp23xx_irq_type irq_type;
+	volatile u32 *int_reg;
+
+	/*
+	 * Only GPIOs 6-15 are wired to interrupts on IXP23xx
+	 */
+	if (line < 6 || line > 15)
+		return -EINVAL;
+
+	switch (type) {
+	case IRQT_BOTHEDGE:
+		int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
+		irq_type = IXP23XX_IRQ_EDGE;
+		break;
+	case IRQT_RISING:
+		int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
+		irq_type = IXP23XX_IRQ_EDGE;
+		break;
+	case IRQT_FALLING:
+		int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
+		irq_type = IXP23XX_IRQ_EDGE;
+		break;
+	case IRQT_HIGH:
+		int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
+		irq_type = IXP23XX_IRQ_LEVEL;
+		break;
+	case IRQT_LOW:
+		int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
+		irq_type = IXP23XX_IRQ_LEVEL;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ixp23xx_config_irq(irq, irq_type);
+
+	if (line >= 8) {	/* pins 8-15 */
+		line -= 8;
+		int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
+	} else {		/* pins 0-7 */
+		int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
+	}
+
+	/*
+	 * Clear pending interrupts
+	 */
+	*IXP23XX_GPIO_GPISR = (1 << line);
+
+	/* Clear the style for the appropriate pin */
+	*int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
+			(line * IXP23XX_GPIO_STYLE_SIZE));
+
+	/* Set the new style */
+	*int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
+
+	return 0;
+}
+
+static void ixp23xx_irq_mask(unsigned int irq)
+{
+	volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
+
+	*intr_reg &= ~(1 << (irq % 32));
+}
+
+static void ixp23xx_irq_ack(unsigned int irq)
+{
+	int line = irq - IRQ_IXP23XX_GPIO6 + 6;
+
+	if ((line < 6) || (line > 15))
+		return;
+
+	*IXP23XX_GPIO_GPISR = (1 << line);
+}
+
+/*
+ * Level triggered interrupts on GPIO lines can only be cleared when the
+ * interrupt condition disappears.
+ */
+static void ixp23xx_irq_level_unmask(unsigned int irq)
+{
+	volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
+
+	ixp23xx_irq_ack(irq);
+
+	*intr_reg |= (1 << (irq % 32));
+}
+
+static void ixp23xx_irq_edge_unmask(unsigned int irq)
+{
+	volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
+
+	*intr_reg |= (1 << (irq % 32));
+}
+
+static struct irqchip ixp23xx_irq_level_chip = {
+	.ack		= ixp23xx_irq_mask,
+	.mask		= ixp23xx_irq_mask,
+	.unmask		= ixp23xx_irq_level_unmask,
+	.set_type	= ixp23xx_irq_set_type
+};
+
+static struct irqchip ixp23xx_irq_edge_chip = {
+	.ack		= ixp23xx_irq_ack,
+	.mask		= ixp23xx_irq_mask,
+	.unmask		= ixp23xx_irq_edge_unmask,
+	.set_type	= ixp23xx_irq_set_type
+};
+
+static void ixp23xx_pci_irq_mask(unsigned int irq)
+{
+	*IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
+}
+
+static void ixp23xx_pci_irq_unmask(unsigned int irq)
+{
+	*IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
+}
+
+/*
+ * TODO: Should this just be done at ASM level?
+ */
+static void pci_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+	u32 pci_interrupt;
+	unsigned int irqno;
+	struct irqdesc *int_desc;
+
+	pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
+
+	desc->chip->ack(irq);
+
+	/* See which PCI_INTA, or PCI_INTB interrupted */
+	if (pci_interrupt & (1 << 26)) {
+		irqno = IRQ_IXP23XX_INTB;
+	} else if (pci_interrupt & (1 << 27)) {
+		irqno = IRQ_IXP23XX_INTA;
+	} else {
+		BUG();
+	}
+
+	int_desc = irq_desc + irqno;
+	int_desc->handle(irqno, int_desc, regs);
+
+	desc->chip->unmask(irq);
+}
+
+static struct irqchip ixp23xx_pci_irq_chip = {
+	.ack	= ixp23xx_pci_irq_mask,
+	.mask	= ixp23xx_pci_irq_mask,
+	.unmask	= ixp23xx_pci_irq_unmask
+};
+
+static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
+{
+	switch (type) {
+	case IXP23XX_IRQ_LEVEL:
+		set_irq_chip(irq, &ixp23xx_irq_level_chip);
+		set_irq_handler(irq, do_level_IRQ);
+		break;
+	case IXP23XX_IRQ_EDGE:
+		set_irq_chip(irq, &ixp23xx_irq_edge_chip);
+		set_irq_handler(irq, do_edge_IRQ);
+		break;
+	}
+	set_irq_flags(irq, IRQF_VALID);
+}
+
+void __init ixp23xx_init_irq(void)
+{
+	int irq;
+
+	/* Route everything to IRQ */
+	*IXP23XX_INTR_SEL1 = 0x0;
+	*IXP23XX_INTR_SEL2 = 0x0;
+	*IXP23XX_INTR_SEL3 = 0x0;
+	*IXP23XX_INTR_SEL4 = 0x0;
+
+	/* Mask all sources */
+	*IXP23XX_INTR_EN1 = 0x0;
+	*IXP23XX_INTR_EN2 = 0x0;
+	*IXP23XX_INTR_EN3 = 0x0;
+	*IXP23XX_INTR_EN4 = 0x0;
+
+	/*
+	 * Configure all IRQs for level-sensitive operation
+	 */
+	for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
+		ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
+	}
+
+	for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
+		set_irq_chip(irq, &ixp23xx_pci_irq_chip);
+		set_irq_handler(irq, do_level_IRQ);
+		set_irq_flags(irq, IRQF_VALID);
+	}
+
+	set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
+}
+
+
+/*************************************************************************
+ * Timer-tick functions for IXP23xx
+ *************************************************************************/
+#define CLOCK_TICKS_PER_USEC	CLOCK_TICK_RATE / (USEC_PER_SEC)
+
+static unsigned long next_jiffy_time;
+
+static unsigned long
+ixp23xx_gettimeoffset(void)
+{
+	unsigned long elapsed;
+
+	elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
+
+	return elapsed / CLOCK_TICKS_PER_USEC;
+}
+
+static irqreturn_t
+ixp23xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	/* Clear Pending Interrupt by writing '1' to it */
+	*IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
+	while ((*IXP23XX_TIMER_CONT - next_jiffy_time) > LATCH) {
+		timer_tick(regs);
+		next_jiffy_time += LATCH;
+	}
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction ixp23xx_timer_irq = {
+	.name		= "IXP23xx Timer Tick",
+	.handler	= ixp23xx_timer_interrupt,
+	.flags		= SA_INTERRUPT | SA_TIMER,
+};
+
+void __init ixp23xx_init_timer(void)
+{
+	/* Clear Pending Interrupt by writing '1' to it */
+	*IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
+
+	/* Setup the Timer counter value */
+	*IXP23XX_TIMER1_RELOAD =
+		(LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
+
+	*IXP23XX_TIMER_CONT = 0;
+	next_jiffy_time = LATCH;
+
+	/* Connect the interrupt handler and enable the interrupt */
+	setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
+}
+
+struct sys_timer ixp23xx_timer = {
+	.init		= ixp23xx_init_timer,
+	.offset		= ixp23xx_gettimeoffset,
+};
+
+
+/*************************************************************************
+ * IXP23xx Platform Initializaion
+ *************************************************************************/
+static struct resource ixp23xx_uart_resources[] = {
+	{
+		.start		= IXP23XX_UART1_PHYS,
+		.end		= IXP23XX_UART1_PHYS + 0x0fff,
+		.flags		= IORESOURCE_MEM
+	}, {
+		.start		= IXP23XX_UART2_PHYS,
+		.end		= IXP23XX_UART2_PHYS + 0x0fff,
+		.flags		= IORESOURCE_MEM
+	}
+};
+
+static struct plat_serial8250_port ixp23xx_uart_data[] = {
+	{
+		.mapbase	= IXP23XX_UART1_PHYS,
+		.membase	= (char *)(IXP23XX_UART1_VIRT + 3),
+		.irq		= IRQ_IXP23XX_UART1,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= IXP23XX_UART_XTAL,
+	}, {
+		.mapbase	= IXP23XX_UART2_PHYS,
+		.membase	= (char *)(IXP23XX_UART2_VIRT + 3),
+		.irq		= IRQ_IXP23XX_UART2,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= IXP23XX_UART_XTAL,
+	},
+	{ },
+};
+
+static struct platform_device ixp23xx_uart = {
+	.name			= "serial8250",
+	.id			= 0,
+	.dev.platform_data	= ixp23xx_uart_data,
+	.num_resources		= 2,
+	.resource		= ixp23xx_uart_resources,
+};
+
+static struct platform_device *ixp23xx_devices[] __initdata = {
+	&ixp23xx_uart,
+};
+
+void __init ixp23xx_sys_init(void)
+{
+	platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
+}
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
new file mode 100644
index 00000000000..2327c979041
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -0,0 +1,69 @@
+/*
+ * arch/arm/mach-ixp23xx/espresso.c
+ *
+ * Double Espresso-specific routines
+ *
+ * Author: Lennert Buytenhek <buytenh@wantstofly.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/bitops.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_core.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/pci.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/tlbflush.h>
+#include <asm/pgtable.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/pci.h>
+
+static void __init espresso_init(void)
+{
+	physmap_configure(0x90000000, 0x02000000, 2, NULL);
+
+	/*
+	 * Mark flash as writeable.
+	 */
+	IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
+	IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
+
+	ixp23xx_sys_init();
+}
+
+MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
+	/* Maintainer: Lennert Buytenhek */
+	.phys_io	= IXP23XX_PERIPHERAL_PHYS,
+	.io_pg_offst	= ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
+	.map_io		= ixp23xx_map_io,
+	.init_irq	= ixp23xx_init_irq,
+	.timer		= &ixp23xx_timer,
+	.boot_params	= 0x00000100,
+	.init_machine	= espresso_init,
+MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
new file mode 100644
index 00000000000..00146c35daa
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -0,0 +1,325 @@
+/*
+ * arch/arm/mach-ixp23xx/ixdp2351.c
+ *
+ * IXDP2351 board-specific routines
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2005 (c) MontaVista Software, Inc.
+ *
+ * Based on 2.4 code Copyright 2004 (c) Intel Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/bitops.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_core.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/pci.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/tlbflush.h>
+#include <asm/pgtable.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/pci.h>
+
+/*
+ * IXDP2351 Interrupt Handling
+ */
+static void ixdp2351_inta_mask(unsigned int irq)
+{
+	*IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(irq);
+}
+
+static void ixdp2351_inta_unmask(unsigned int irq)
+{
+	*IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
+}
+
+static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+	u16 ex_interrupt =
+		*IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
+	int i;
+
+	desc->chip->mask(irq);
+
+	for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
+		if (ex_interrupt & (1 << i)) {
+			struct irqdesc *cpld_desc;
+			int cpld_irq =
+				IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
+			cpld_desc = irq_desc + cpld_irq;
+			cpld_desc->handle(cpld_irq, cpld_desc, regs);
+		}
+	}
+
+	desc->chip->unmask(irq);
+}
+
+static struct irqchip ixdp2351_inta_chip = {
+	.ack	= ixdp2351_inta_mask,
+	.mask	= ixdp2351_inta_mask,
+	.unmask	= ixdp2351_inta_unmask
+};
+
+static void ixdp2351_intb_mask(unsigned int irq)
+{
+	*IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(irq);
+}
+
+static void ixdp2351_intb_unmask(unsigned int irq)
+{
+	*IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
+}
+
+static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+{
+	u16 ex_interrupt =
+		*IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
+	int i;
+
+	desc->chip->ack(irq);
+
+	for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
+		if (ex_interrupt & (1 << i)) {
+			struct irqdesc *cpld_desc;
+			int cpld_irq =
+				IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
+			cpld_desc = irq_desc + cpld_irq;
+			cpld_desc->handle(cpld_irq, cpld_desc, regs);
+		}
+	}
+
+	desc->chip->unmask(irq);
+}
+
+static struct irqchip ixdp2351_intb_chip = {
+	.ack	= ixdp2351_intb_mask,
+	.mask	= ixdp2351_intb_mask,
+	.unmask	= ixdp2351_intb_unmask
+};
+
+void ixdp2351_init_irq(void)
+{
+	int irq;
+
+	/* Mask all interrupts from CPLD, disable simulation */
+	*IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
+	*IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
+	*IXDP2351_CPLD_INTA_SIM_REG = 0;
+	*IXDP2351_CPLD_INTB_SIM_REG = 0;
+
+	ixp23xx_init_irq();
+
+	for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
+	     irq <
+	     IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
+	     irq++) {
+		if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
+			set_irq_flags(irq, IRQF_VALID);
+			set_irq_handler(irq, do_level_IRQ);
+			set_irq_chip(irq, &ixdp2351_inta_chip);
+		}
+	}
+
+	for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
+	     irq <
+	     IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
+	     irq++) {
+		if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
+			set_irq_flags(irq, IRQF_VALID);
+			set_irq_handler(irq, do_level_IRQ);
+			set_irq_chip(irq, &ixdp2351_intb_chip);
+		}
+	}
+
+	set_irq_chained_handler(IRQ_IXP23XX_INTA, &ixdp2351_inta_handler);
+	set_irq_chained_handler(IRQ_IXP23XX_INTB, &ixdp2351_intb_handler);
+}
+
+/*
+ * IXDP2351 PCI
+ */
+
+/*
+ * This board does not do normal PCI IRQ routing, or any
+ * sort of swizzling, so we just need to check where on the
+ * bus the device is and figure out what CPLD pin it is
+ * being routed to.
+ */
+#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
+
+static int __init ixdp2351_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	u8 bus = dev->bus->number;
+	u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
+	struct pci_bus *tmp_bus = dev->bus;
+
+	/* Primary bus, no interrupts here */
+	if (!bus)
+		return -1;
+
+	/* Lookup first leaf in bus tree */
+	while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL))
+		tmp_bus = tmp_bus->parent;
+
+	/* Select between known bridges */
+	switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
+		/* Device is located after first bridge */
+	case 0x0008:
+		if (tmp_bus == dev->bus) {
+			/* Device is located directy after first bridge */
+			switch (devpin) {
+				/* Onboard 82546 */
+			case DEVPIN(1, 1):	/* Onboard 82546 ch 0 */
+				return IRQ_IXDP2351_INTA_82546;
+			case DEVPIN(1, 2):	/* Onboard 82546 ch 1 */
+				return IRQ_IXDP2351_INTB_82546;
+				/* PMC SLOT */
+			case DEVPIN(0, 1):	/* PMCP INTA# */
+			case DEVPIN(2, 4):	/* PMCS INTD# */
+				return IRQ_IXDP2351_SPCI_PMC_INTA;
+			case DEVPIN(0, 2):	/* PMCP INTB# */
+			case DEVPIN(2, 1):	/* PMCS INTA# */
+				return IRQ_IXDP2351_SPCI_PMC_INTB;
+			case DEVPIN(0, 3):	/* PMCP INTC# */
+			case DEVPIN(2, 2):	/* PMCS INTB# */
+				return IRQ_IXDP2351_SPCI_PMC_INTC;
+			case DEVPIN(0, 4):	/* PMCP INTD# */
+			case DEVPIN(2, 3):	/* PMCS INTC# */
+				return IRQ_IXDP2351_SPCI_PMC_INTD;
+			}
+		} else {
+			/* Device is located indirectly after first bridge */
+			/* Not supported now */
+			return -1;
+		}
+		break;
+	case 0x0010:
+		if (tmp_bus == dev->bus) {
+			/* Device is located directy after second bridge */
+			/* Secondary bus of second bridge */
+			switch (devpin) {
+			case DEVPIN(0, 1):	/* DB#0 */
+			case DEVPIN(0, 2):
+			case DEVPIN(0, 3):
+			case DEVPIN(0, 4):
+				return IRQ_IXDP2351_SPCI_DB_0;
+			case DEVPIN(1, 1):	/* DB#1 */
+			case DEVPIN(1, 2):
+			case DEVPIN(1, 3):
+			case DEVPIN(1, 4):
+				return IRQ_IXDP2351_SPCI_DB_1;
+			case DEVPIN(2, 1):	/* FIC1 */
+			case DEVPIN(2, 2):
+			case DEVPIN(2, 3):
+			case DEVPIN(2, 4):
+			case DEVPIN(3, 1):	/* FIC2 */
+			case DEVPIN(3, 2):
+			case DEVPIN(3, 3):
+			case DEVPIN(3, 4):
+				return IRQ_IXDP2351_SPCI_FIC;
+			}
+		} else {
+			/* Device is located indirectly after second bridge */
+			/* Not supported now */
+			return -1;
+		}
+		break;
+	}
+
+	return -1;
+}
+
+struct hw_pci ixdp2351_pci __initdata = {
+	.nr_controllers	= 1,
+	.preinit	= ixp23xx_pci_preinit,
+	.setup		= ixp23xx_pci_setup,
+	.scan		= ixp23xx_pci_scan_bus,
+	.map_irq	= ixdp2351_map_irq,
+};
+
+int __init ixdp2351_pci_init(void)
+{
+	if (machine_is_ixdp2351())
+		pci_common_init(&ixdp2351_pci);
+
+	return 0;
+}
+
+subsys_initcall(ixdp2351_pci_init);
+
+/*
+ * IXDP2351 Static Mapped I/O
+ */
+static struct map_desc ixdp2351_io_desc[] __initdata = {
+	{
+		.virtual	= IXDP2351_NP_VIRT_BASE,
+		.pfn		= __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE),
+		.length		= IXDP2351_NP_PHYS_SIZE,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	= IXDP2351_BB_BASE_VIRT,
+		.pfn		= __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS),
+		.length		= IXDP2351_BB_SIZE,
+		.type		= MT_DEVICE
+	}
+};
+
+static void __init ixdp2351_map_io(void)
+{
+	ixp23xx_map_io();
+	iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc));
+}
+
+static void __init ixdp2351_init(void)
+{
+	physmap_configure(0x90000000, 0x04000000, 1, NULL);
+
+	/*
+	 * Mark flash as writeable
+	 */
+	IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
+	IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
+	IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
+	IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
+
+	ixp23xx_sys_init();
+}
+
+MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
+	/* Maintainer: MontaVista Software, Inc. */
+	.phys_io	= IXP23XX_PERIPHERAL_PHYS,
+	.io_pg_offst	= ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
+	.map_io		= ixdp2351_map_io,
+	.init_irq	= ixdp2351_init_irq,
+	.timer		= &ixp23xx_timer,
+	.boot_params	= 0x00000100,
+	.init_machine	= ixdp2351_init,
+MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
new file mode 100644
index 00000000000..5330ad78c1b
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -0,0 +1,275 @@
+/*
+ * arch/arm/mach-ixp23xx/pci.c
+ *
+ * PCI routines for IXP23XX based systems
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ *
+ * based on original code:
+ *
+ * Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Copyright 2002-2005 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/sizes.h>
+#include <asm/system.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+#include <asm/hardware.h>
+
+extern int (*external_fault) (unsigned long, struct pt_regs *);
+
+static int pci_master_aborts = 0;
+
+#ifdef DEBUG
+#define DBG(x...)	printk(x)
+#else
+#define DBG(x...)
+#endif
+
+int clear_master_aborts(void);
+
+static u32
+*ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
+{
+	u32 *paddress;
+
+	/*
+	 * Must be dword aligned
+	 */
+	where &= ~3;
+
+	/*
+	 * For top bus, generate type 0, else type 1
+	 */
+	if (!bus_nr) {
+		if (PCI_SLOT(devfn) >= 8)
+			return 0;
+
+		paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
+				    | (1 << (PCI_SLOT(devfn) + 16))
+				    | (PCI_FUNC(devfn) << 8) | where);
+	} else {
+		paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
+				    | (bus_nr << 16)
+				    | (PCI_SLOT(devfn) << 11)
+				    | (PCI_FUNC(devfn) << 8) | where);
+	}
+
+	return paddress;
+}
+
+/*
+ * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
+ * 0 and 3 are not valid indexes...
+ */
+static u32 bytemask[] = {
+	/*0*/	0,
+	/*1*/	0xff,
+	/*2*/	0xffff,
+	/*3*/	0,
+	/*4*/	0xffffffff,
+};
+
+static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+				int where, int size, u32 *value)
+{
+	u32 n;
+	u32 *addr;
+
+	n = where % 4;
+
+	DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
+		bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
+
+	addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
+	if (!addr)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	pci_master_aborts = 0;
+	*value = (*addr >> (8*n)) & bytemask[size];
+	if (pci_master_aborts) {
+			pci_master_aborts = 0;
+			*value = 0xffffffff;
+			return PCIBIOS_DEVICE_NOT_FOUND;
+		}
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+/*
+ * We don't do error checking on the address for writes.
+ * It's assumed that the user checked for the device existing first
+ * by doing a read first.
+ */
+static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+					int where, int size, u32 value)
+{
+	u32 mask;
+	u32 *addr;
+	u32 temp;
+
+	mask = ~(bytemask[size] << ((where % 0x4) * 8));
+	addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
+	if (!addr)
+		return PCIBIOS_DEVICE_NOT_FOUND;
+	temp = (u32) (value) << ((where % 0x4) * 8);
+	*addr = (*addr & mask) | temp;
+
+	clear_master_aborts();
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops ixp23xx_pci_ops = {
+	.read	= ixp23xx_pci_read_config,
+	.write	= ixp23xx_pci_write_config,
+};
+
+struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
+{
+	return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
+}
+
+int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+{
+	volatile unsigned long temp;
+	unsigned long flags;
+
+	pci_master_aborts = 1;
+
+	local_irq_save(flags);
+	temp = *IXP23XX_PCI_CONTROL;
+
+	/*
+	 * master abort and cmd tgt err
+	 */
+	if (temp & ((1 << 8) | (1 << 5)))
+		*IXP23XX_PCI_CONTROL = temp;
+
+	temp = *IXP23XX_PCI_CMDSTAT;
+
+	if (temp & (1 << 29))
+		*IXP23XX_PCI_CMDSTAT = temp;
+	local_irq_restore(flags);
+
+	/*
+	 * If it was an imprecise abort, then we need to correct the
+	 * return address to be _after_ the instruction.
+	 */
+	if (fsr & (1 << 10))
+		regs->ARM_pc += 4;
+
+	return 0;
+}
+
+int clear_master_aborts(void)
+{
+	volatile u32 temp;
+
+	temp = *IXP23XX_PCI_CONTROL;
+
+	/*
+	 * master abort and cmd tgt err
+	 */
+	if (temp & ((1 << 8) | (1 << 5)))
+		*IXP23XX_PCI_CONTROL = temp;
+
+	temp = *IXP23XX_PCI_CMDSTAT;
+
+	if (temp & (1 << 29))
+		*IXP23XX_PCI_CMDSTAT = temp;
+
+	return 0;
+}
+
+void __init ixp23xx_pci_preinit(void)
+{
+#ifdef __ARMEB__
+	*IXP23XX_PCI_CONTROL |= 0x20000;	/* set I/O swapping */
+#endif
+	/*
+	 * ADDR_31 needs to be clear for PCI memory access to CPP memory
+	 */
+	*IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
+	*IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
+
+	/*
+	 * Select correct memory for PCI inbound transactions
+	 */
+	if (ixp23xx_cpp_boot()) {
+		*IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
+	} else {
+		*IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
+	}
+
+	hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS,
+			"PCI config cycle to non-existent device");
+
+	*IXP23XX_PCI_ADDR_EXT = 0x0000e000;
+}
+
+/*
+ * Prevent PCI layer from seeing the inbound host-bridge resources
+ */
+static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
+{
+	int i;
+
+	dev->class &= 0xff;
+	dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
+	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+		dev->resource[i].start = 0;
+		dev->resource[i].end   = 0;
+		dev->resource[i].flags = 0;
+	}
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
+
+/*
+ * IXP2300 systems often have large resource requirements, so we just
+ * use our own resource space.
+ */
+static struct resource ixp23xx_pci_mem_space = {
+	.start	= IXP23XX_PCI_MEM_START,
+	.end	= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
+	.flags	= IORESOURCE_MEM,
+	.name	= "PCI Mem Space"
+};
+
+static struct resource ixp23xx_pci_io_space = {
+	.start	= 0x00000100,
+	.end	= 0x01ffffff,
+	.flags	= IORESOURCE_IO,
+	.name	= "PCI I/O Space"
+};
+
+int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
+{
+	if (nr >= 1)
+		return 0;
+
+	sys->resource[0] = &ixp23xx_pci_io_space;
+	sys->resource[1] = &ixp23xx_pci_mem_space;
+	sys->resource[2] = NULL;
+
+	return 1;
+}
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
new file mode 100644
index 00000000000..43c14e74079
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -0,0 +1,164 @@
+/*
+ * arch/arm/mach-ixp23xx/roadrunner.c
+ *
+ * RoadRunner board-specific routines
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2005 (c) MontaVista Software, Inc.
+ *
+ * Based on 2.4 code Copyright 2005 (c) ADI Engineering Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/serial.h>
+#include <linux/tty.h>
+#include <linux/bitops.h>
+#include <linux/ioport.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/serial_core.h>
+#include <linux/device.h>
+#include <linux/mm.h>
+#include <linux/pci.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/types.h>
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/tlbflush.h>
+#include <asm/pgtable.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/pci.h>
+
+/*
+ * Interrupt mapping
+ */
+#define INTA		IRQ_ROADRUNNER_PCI_INTA
+#define INTB		IRQ_ROADRUNNER_PCI_INTB
+#define INTC		IRQ_ROADRUNNER_PCI_INTC
+#define INTD		IRQ_ROADRUNNER_PCI_INTD
+
+#define INTC_PIN	IXP23XX_GPIO_PIN_11
+#define INTD_PIN	IXP23XX_GPIO_PIN_12
+
+static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+	static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA};
+	static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD};
+	static int usb_irq[] = {INTB, INTC, INTD, -1};
+	static int mini_pci_1_irq[] = {INTB, INTC, -1, -1};
+	static int mini_pci_2_irq[] = {INTC, INTD, -1, -1};
+
+	switch(dev->bus->number) {
+		case 0:
+			switch(dev->devfn) {
+			case 0x0: // PCI-PCI bridge
+				break;
+			case 0x8: // PCI Card Slot
+				return pci_card_slot_irq[pin - 1];
+			case 0x10: // PMC Slot
+				return pmc_card_slot_irq[pin - 1];
+			case 0x18: // PMC Slot Secondary Agent
+				break;
+			case 0x20: // IXP Processor
+				break;
+			default:
+				return NO_IRQ;
+			}
+			break;
+
+		case 1:
+			switch(dev->devfn) {
+			case 0x0: // IDE Controller
+				return (pin == 1) ? INTC : -1;
+			case 0x8: // USB fun 0
+			case 0x9: // USB fun 1
+			case 0xa: // USB fun 2
+				return usb_irq[pin - 1];
+			case 0x10: // Mini PCI 1
+				return mini_pci_1_irq[pin-1];
+			case 0x18: // Mini PCI 2
+				return mini_pci_2_irq[pin-1];
+			case 0x20: // MEM slot
+				return (pin == 1) ? INTA : -1;
+			default:
+				return NO_IRQ;
+			}
+			break;
+
+		default:
+			return NO_IRQ;
+	}
+
+	return NO_IRQ;
+}
+
+static void roadrunner_pci_preinit(void)
+{
+	set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQT_LOW);
+	set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQT_LOW);
+
+	ixp23xx_pci_preinit();
+}
+
+static struct hw_pci roadrunner_pci __initdata = {
+	.nr_controllers	= 1,
+	.preinit	= roadrunner_pci_preinit,
+	.setup		= ixp23xx_pci_setup,
+	.scan		= ixp23xx_pci_scan_bus,
+	.map_irq	= roadrunner_map_irq,
+};
+
+static int __init roadrunner_pci_init(void)
+{
+	if (machine_is_roadrunner())
+		pci_common_init(&roadrunner_pci);
+
+	return 0;
+};
+
+subsys_initcall(roadrunner_pci_init);
+
+static void __init roadrunner_init(void)
+{
+	physmap_configure(0x90000000, 0x04000000, 2, NULL);
+
+	/*
+	 * Mark flash as writeable
+	 */
+	IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
+	IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
+	IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
+	IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
+
+	ixp23xx_sys_init();
+}
+
+MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
+	/* Maintainer: Deepak Saxena */
+	.phys_io	= IXP23XX_PERIPHERAL_PHYS,
+	.io_pg_offst	= ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
+	.map_io		= ixp23xx_map_io,
+	.init_irq	= ixp23xx_init_irq,
+	.timer		= &ixp23xx_timer,
+	.boot_params	= 0x00000100,
+	.init_machine	= roadrunner_init,
+MACHINE_END