[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach

This just leaves include/asm-arm/plat-* to deal with.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

24 files changed, 1505 insertions, 9 deletions

diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 7e810b3fa55..a6a4f93085f 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -29,7 +29,7 @@
 #include <asm/types.h>
 #include <asm/setup.h>
 #include <asm/memory.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
@@ -39,7 +39,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
-#include <asm/arch/gpio.h>
+#include <mach/gpio.h>
 
 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
 static unsigned long ixp2000_slowport_irq_flags;
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index 17af9f7bd06..c62ed655c1a 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -38,7 +38,7 @@
 #include <asm/pgtable.h>
 #include <asm/page.h>
 #include <asm/system.h>
-#include <asm/arch/hardware.h>
+#include <mach/hardware.h>
 #include <asm/mach-types.h>
 
 #include <asm/mach/pci.h>
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
new file mode 100644
index 00000000000..904ff56d224
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
@@ -0,0 +1,27 @@
+/* arch/arm/mach-ixp2000/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+		.macro  addruart,rx
+		mrc	p15, 0, \rx, c1, c0
+		tst	\rx, #1			@ MMU enabled?
+		moveq	\rx, #0xc0000000	@ Physical base
+		movne	\rx, #0xfe000000	@ virtual base
+		orrne	\rx, \rx, #0x00f00000
+		orr	\rx, \rx, #0x00030000
+#ifdef	__ARMEB__
+		orr	\rx, \rx, #0x00000003
+#endif
+		.endm
+
+#define UART_SHIFT	2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ixp2000/include/mach/dma.h b/arch/arm/mach-ixp2000/include/mach/dma.h
new file mode 100644
index 00000000000..26063d60f62
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/dma.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/dma.h
+ *
+ * Copyright (C) 2002 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
diff --git a/arch/arm/mach-ixp2000/include/mach/enp2611.h b/arch/arm/mach-ixp2000/include/mach/enp2611.h
new file mode 100644
index 00000000000..9ce3690061d
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/enp2611.h
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/enp2611.h
+ *
+ * Register and other defines for Radisys ENP-2611
+ *
+ * Created 2004 by Lennert Buytenhek from the ixdp2x01 code.  The
+ * original version carries the following notices:
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __ENP2611_H
+#define __ENP2611_H
+
+#define ENP2611_CALEB_PHYS_BASE		0xc5000000
+#define ENP2611_CALEB_VIRT_BASE		0xfe000000
+#define ENP2611_CALEB_SIZE		0x00100000
+
+#define ENP2611_PM3386_0_PHYS_BASE	0xc6000000
+#define ENP2611_PM3386_0_VIRT_BASE	0xfe100000
+#define ENP2611_PM3386_0_SIZE		0x00100000
+
+#define ENP2611_PM3386_1_PHYS_BASE	0xc6400000
+#define ENP2611_PM3386_1_VIRT_BASE	0xfe200000
+#define ENP2611_PM3386_1_SIZE		0x00100000
+
+#define ENP2611_GPIO_SCL		7
+#define ENP2611_GPIO_SDA		6
+
+#define IRQ_ENP2611_THERMAL		IRQ_IXP2000_GPIO4
+#define IRQ_ENP2611_OPTION_BOARD	IRQ_IXP2000_GPIO3
+#define IRQ_ENP2611_CALEB		IRQ_IXP2000_GPIO2
+#define IRQ_ENP2611_PM3386_1		IRQ_IXP2000_GPIO1
+#define IRQ_ENP2611_PM3386_0		IRQ_IXP2000_GPIO0
+
+
+#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
new file mode 100644
index 00000000000..5850ffc8c75
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/entry-macro.S
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IXP2000-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/irqs.h>
+
+		.macro  disable_fiq
+		.endm
+
+		.macro  get_irqnr_preamble, base, tmp
+		.endm
+
+		.macro  arch_ret_to_user, tmp1, tmp2
+		.endm
+
+		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+		mov	\irqnr, #0x0              @clear out irqnr as default
+                mov	\base, #0xfe000000
+		orr	\base, \base, #0x00e00000
+		orr	\base, \base, #0x08
+		ldr	\irqstat, [\base]         @ get interrupts
+
+		cmp	\irqstat, #0
+		beq	1001f
+
+		clz     \irqnr, \irqstat
+		mov     \base, #31
+		subs    \irqnr, \base, \irqnr
+
+		/*
+		 * We handle PCIA and PCIB here so we don't have an
+		 * extra layer of code just to check these two bits.
+		 */
+		cmp	\irqnr, #IRQ_IXP2000_PCI
+		bne	1001f
+
+		mov	\base, #0xfe000000
+		orr	\base, \base, #0x00c00000
+		orr	\base, \base, #0x00000100
+		orr	\base, \base, #0x00000058
+		ldr	\irqstat, [\base]
+
+		mov	\tmp, #(1<<26)
+		tst	\irqstat, \tmp
+		movne	\irqnr, #IRQ_IXP2000_PCIA
+		bne	1001f
+
+		mov	\tmp, #(1<<27)
+		tst	\irqstat, \tmp
+		movne	\irqnr, #IRQ_IXP2000_PCIB
+
+1001:
+		.endm
+
diff --git a/arch/arm/mach-ixp2000/include/mach/gpio.h b/arch/arm/mach-ixp2000/include/mach/gpio.h
new file mode 100644
index 00000000000..4a88d2c33da
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/gpio.h
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/gpio.h
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ *
+ * This program is free software, you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * IXP2000 GPIO in/out, edge/level detection for IRQs:
+ * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
+ * or both Falling-edge and Rising-edge.  
+ * This must be called *before* the corresponding IRQ is registerd.
+ * Use this instead of directly setting the GPIO registers.
+ * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
+ */
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+
+#define GPIO_IN				0
+#define GPIO_OUT			1
+
+#define IXP2000_GPIO_LOW		0
+#define IXP2000_GPIO_HIGH		1
+
+extern void gpio_line_config(int line, int direction);
+
+static inline int gpio_line_get(int line)
+{
+	return (((*IXP2000_GPIO_PLR) >> line) & 1);
+}
+
+static inline void gpio_line_set(int line, int value)
+{
+	if (value == IXP2000_GPIO_HIGH) {
+		ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
+	} else if (value == IXP2000_GPIO_LOW) {
+		ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
+	}
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h
new file mode 100644
index 00000000000..f033de4e749
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/hardware.h
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/hardware.h
+ *
+ * Hardware definitions for IXP2400/2800 based systems
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ *
+ * Maintainer: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright (C) 2001-2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#define __ASM_ARCH_HARDWARE_H__
+
+/*
+ * This needs to be platform-specific?
+ */
+#define PCIBIOS_MIN_IO          0x00000000
+#define PCIBIOS_MIN_MEM         0x00000000
+
+#include "ixp2000-regs.h"	/* Chipset Registers */
+
+#define pcibios_assign_all_busses() 0
+
+/*
+ * Platform helper functions
+ */
+#include "platform.h"
+
+/*
+ * Platform-specific bits
+ */
+#include "enp2611.h"		/* ENP-2611 */
+#include "ixdp2x00.h"		/* IXDP2400/2800 */
+#include "ixdp2x01.h"		/* IXDP2401/2801 */
+
+#endif  /* _ASM_ARCH_HARDWARE_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h
new file mode 100644
index 00000000000..859e584914d
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/io.h
@@ -0,0 +1,134 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/io.h
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002  Intel Corp.
+ * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <mach/hardware.h>
+
+#define IO_SPACE_LIMIT		0xffffffff
+#define __mem_pci(a)		(a)
+
+/*
+ * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
+ * transactions the other way round (MEM transactions don't have this
+ * issue), so if we want to support those models, we need to override
+ * the standard I/O functions.
+ *
+ * B0 and later have a bit that can be set to 1 to get the proper
+ * behavior for I/O transactions, which then allows us to use the
+ * standard I/O functions.  This is what we do if the user does not
+ * explicitly ask for support for pre-B0.
+ */
+#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
+#define ___io(p)		((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+
+#define alignb(addr)		(void __iomem *)((unsigned long)(addr) ^ 3)
+#define alignw(addr)		(void __iomem *)((unsigned long)(addr) ^ 2)
+
+#define outb(v,p)		__raw_writeb((v),alignb(___io(p)))
+#define outw(v,p)		__raw_writew((v),alignw(___io(p)))
+#define outl(v,p)		__raw_writel((v),___io(p))
+
+#define inb(p)		({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
+#define inw(p)		\
+	({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
+#define inl(p)		\
+	({ unsigned int __v = (__raw_readl(___io(p))); __v; })
+
+#define outsb(p,d,l)		__raw_writesb(alignb(___io(p)),d,l)
+#define outsw(p,d,l)		__raw_writesw(alignw(___io(p)),d,l)
+#define outsl(p,d,l)		__raw_writesl(___io(p),d,l)
+
+#define insb(p,d,l)		__raw_readsb(alignb(___io(p)),d,l)
+#define insw(p,d,l)		__raw_readsw(alignw(___io(p)),d,l)
+#define insl(p,d,l)		__raw_readsl(___io(p),d,l)
+
+#define __is_io_address(p)	((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
+
+#define ioread8(p)						\
+	({							\
+		unsigned int __v;				\
+								\
+		if (__is_io_address(p)) {			\
+			__v = __raw_readb(alignb(p));		\
+		} else {					\
+			__v = __raw_readb(p);			\
+		}						\
+								\
+		__v;						\
+	})							\
+
+#define ioread16(p)						\
+	({							\
+		unsigned int __v;				\
+								\
+		if (__is_io_address(p)) {			\
+			__v = __raw_readw(alignw(p));		\
+		} else {					\
+			__v = le16_to_cpu(__raw_readw(p));	\
+		}						\
+								\
+		__v;						\
+	})
+
+#define ioread32(p)						\
+	({							\
+		unsigned int __v;				\
+								\
+		if (__is_io_address(p)) {			\
+			__v = __raw_readl(p);			\
+		} else {					\
+			__v = le32_to_cpu(__raw_readl(p));	\
+		}						\
+								\
+		 __v;						\
+	})
+
+#define iowrite8(v,p)						\
+	({							\
+		if (__is_io_address(p)) {			\
+			__raw_writeb((v), alignb(p));		\
+		} else {					\
+			__raw_writeb((v), p);			\
+		}						\
+	})
+
+#define iowrite16(v,p)						\
+	({							\
+		if (__is_io_address(p)) {			\
+			__raw_writew((v), alignw(p));		\
+		} else {					\
+			__raw_writew(cpu_to_le16(v), p);	\
+		}						\
+	})
+
+#define iowrite32(v,p)						\
+	({							\
+		if (__is_io_address(p)) {			\
+			__raw_writel((v), p);			\
+		} else {					\
+			__raw_writel(cpu_to_le32(v), p);	\
+		}						\
+	})
+
+#define ioport_map(port, nr)	___io(port)
+
+#define ioport_unmap(addr)
+#else
+#define __io(p)			((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+#endif
+
+
+#endif
diff --git a/arch/arm/mach-ixp2000/include/mach/irqs.h b/arch/arm/mach-ixp2000/include/mach/irqs.h
new file mode 100644
index 00000000000..bee96bcafdc
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/irqs.h
@@ -0,0 +1,207 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/irqs.h
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IRQS_H
+#define _IRQS_H
+
+/*
+ * Do NOT add #ifdef MACHINE_FOO in here.
+ * Simpy add your machine IRQs here and increase NR_IRQS if needed to
+ * hold your machine's IRQ table.
+ */
+
+/*
+ * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
+ * register has those bit reserved. We just mark those interrupts
+ * as invalid and this allows us to do mask/unmask with a single
+ * shift operation instead of having to map the IRQ number to
+ * a HW IRQ number.
+ */
+#define	IRQ_IXP2000_SOFT_INT		0 /* soft interrupt */
+#define	IRQ_IXP2000_ERRSUM		1 /* OR of all bits in ErrorStatus reg*/
+#define	IRQ_IXP2000_UART		2
+#define	IRQ_IXP2000_GPIO		3
+#define	IRQ_IXP2000_TIMER1     		4
+#define	IRQ_IXP2000_TIMER2     		5
+#define	IRQ_IXP2000_TIMER3     		6
+#define	IRQ_IXP2000_TIMER4     		7
+#define	IRQ_IXP2000_PMU        		8               
+#define	IRQ_IXP2000_SPF        		9  /* Slow port framer IRQ */
+#define	IRQ_IXP2000_DMA1      		10
+#define	IRQ_IXP2000_DMA2      		11
+#define	IRQ_IXP2000_DMA3      		12
+#define	IRQ_IXP2000_PCI_DOORBELL	13
+#define	IRQ_IXP2000_ME_ATTN       	14 
+#define	IRQ_IXP2000_PCI   		15 /* PCI INTA or INTB */
+#define	IRQ_IXP2000_THDA0   		16 /* thread 0-31A */
+#define	IRQ_IXP2000_THDA1  		17 /* thread 32-63A, IXP2800 only */
+#define	IRQ_IXP2000_THDA2		18 /* thread 64-95A */
+#define	IRQ_IXP2000_THDA3 		19 /* thread 96-127A, IXP2800 only */
+#define	IRQ_IXP2000_THDB0		24 /* thread 0-31B */
+#define	IRQ_IXP2000_THDB1		25 /* thread 32-63B, IXP2800 only */
+#define	IRQ_IXP2000_THDB2		26 /* thread 64-95B */
+#define	IRQ_IXP2000_THDB3		27 /* thread 96-127B, IXP2800 only */
+
+/* define generic GPIOs */
+#define IRQ_IXP2000_GPIO0		32
+#define IRQ_IXP2000_GPIO1		33
+#define IRQ_IXP2000_GPIO2		34
+#define IRQ_IXP2000_GPIO3		35
+#define IRQ_IXP2000_GPIO4		36
+#define IRQ_IXP2000_GPIO5		37
+#define IRQ_IXP2000_GPIO6		38
+#define IRQ_IXP2000_GPIO7		39
+
+/* split off the 2 PCI sources */
+#define IRQ_IXP2000_PCIA		40
+#define IRQ_IXP2000_PCIB		41
+
+/* Int sources from IRQ_ERROR_STATUS */
+#define IRQ_IXP2000_DRAM0_MIN_ERR	42
+#define IRQ_IXP2000_DRAM0_MAJ_ERR	43
+#define IRQ_IXP2000_DRAM1_MIN_ERR	44
+#define IRQ_IXP2000_DRAM1_MAJ_ERR	45
+#define IRQ_IXP2000_DRAM2_MIN_ERR	46
+#define IRQ_IXP2000_DRAM2_MAJ_ERR	47
+/* 48-57 reserved */
+#define IRQ_IXP2000_SRAM0_ERR		58
+#define IRQ_IXP2000_SRAM1_ERR		59
+#define IRQ_IXP2000_SRAM2_ERR		60
+#define IRQ_IXP2000_SRAM3_ERR		61
+/* 62-65 reserved */
+#define IRQ_IXP2000_MEDIA_ERR		66
+#define IRQ_IXP2000_PCI_ERR			67
+#define IRQ_IXP2000_SP_INT			68
+
+#define NR_IXP2000_IRQS				69
+
+#define	IXP2000_BOARD_IRQ(x)		(NR_IXP2000_IRQS + (x))
+
+#define	IXP2000_BOARD_IRQ_MASK(irq)	(1 << (irq - NR_IXP2000_IRQS))	
+
+#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
+#define IXP2000_VALID_ERR_IRQ_MASK (\
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
+		IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT)	)
+
+/*
+ * This allows for all the on-chip sources plus up to 32 CPLD based
+ * IRQs. Should be more than enough.
+ */
+#define	IXP2000_BOARD_IRQS		32
+#define NR_IRQS				(NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
+
+
+/* 
+ * IXDP2400 specific IRQs
+ */
+#define	IRQ_IXDP2400_INGRESS_NPU	IXP2000_BOARD_IRQ(0) 
+#define	IRQ_IXDP2400_ENET		IXP2000_BOARD_IRQ(1) 
+#define	IRQ_IXDP2400_MEDIA_PCI		IXP2000_BOARD_IRQ(2) 
+#define	IRQ_IXDP2400_MEDIA_SP		IXP2000_BOARD_IRQ(3) 
+#define	IRQ_IXDP2400_SF_PCI		IXP2000_BOARD_IRQ(4) 
+#define	IRQ_IXDP2400_SF_SP		IXP2000_BOARD_IRQ(5) 
+#define	IRQ_IXDP2400_PMC		IXP2000_BOARD_IRQ(6) 
+#define	IRQ_IXDP2400_TVM		IXP2000_BOARD_IRQ(7) 
+
+#define	NR_IXDP2400_IRQS		((IRQ_IXDP2400_TVM)+1)  
+#define	IXDP2400_NR_IRQS		NR_IXDP2400_IRQS - NR_IXP2000_IRQS
+
+/* IXDP2800 specific IRQs */
+#define IRQ_IXDP2800_EGRESS_ENET	IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2800_INGRESS_NPU	IXP2000_BOARD_IRQ(1)
+#define IRQ_IXDP2800_PMC		IXP2000_BOARD_IRQ(2)
+#define IRQ_IXDP2800_FABRIC_PCI		IXP2000_BOARD_IRQ(3)
+#define IRQ_IXDP2800_FABRIC		IXP2000_BOARD_IRQ(4)
+#define IRQ_IXDP2800_MEDIA		IXP2000_BOARD_IRQ(5)
+
+#define	NR_IXDP2800_IRQS		((IRQ_IXDP2800_MEDIA)+1)
+#define	IXDP2800_NR_IRQS		NR_IXDP2800_IRQS - NR_IXP2000_IRQS
+
+/* 
+ * IRQs on both IXDP2x01 boards
+ */
+#define IRQ_IXDP2X01_SPCI_DB_0		IXP2000_BOARD_IRQ(2)
+#define IRQ_IXDP2X01_SPCI_DB_1		IXP2000_BOARD_IRQ(3)
+#define IRQ_IXDP2X01_SPCI_PMC_INTA	IXP2000_BOARD_IRQ(4)
+#define IRQ_IXDP2X01_SPCI_PMC_INTB	IXP2000_BOARD_IRQ(5)
+#define IRQ_IXDP2X01_SPCI_PMC_INTC	IXP2000_BOARD_IRQ(6)
+#define IRQ_IXDP2X01_SPCI_PMC_INTD	IXP2000_BOARD_IRQ(7)
+#define IRQ_IXDP2X01_SPCI_FIC_INT	IXP2000_BOARD_IRQ(8)
+#define IRQ_IXDP2X01_IPMI_FROM		IXP2000_BOARD_IRQ(16)
+#define IRQ_IXDP2X01_125US		IXP2000_BOARD_IRQ(17)
+#define IRQ_IXDP2X01_DB_0_ADD		IXP2000_BOARD_IRQ(18)
+#define IRQ_IXDP2X01_DB_1_ADD		IXP2000_BOARD_IRQ(19)
+#define IRQ_IXDP2X01_UART1		IXP2000_BOARD_IRQ(21)
+#define IRQ_IXDP2X01_UART2		IXP2000_BOARD_IRQ(22)
+#define IRQ_IXDP2X01_FIC_ADD_INT	IXP2000_BOARD_IRQ(24)
+#define IRQ_IXDP2X01_CS8900		IXP2000_BOARD_IRQ(25)
+#define IRQ_IXDP2X01_BBSRAM		IXP2000_BOARD_IRQ(26)
+
+#define IXDP2X01_VALID_IRQ_MASK ( \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
+
+/* 
+ * IXDP2401 specific IRQs
+ */
+#define IRQ_IXDP2401_INTA_82546		IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2401_INTB_82546		IXP2000_BOARD_IRQ(1)
+
+#define	IXDP2401_VALID_IRQ_MASK ( \
+		IXDP2X01_VALID_IRQ_MASK | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
+
+/*
+ * IXDP2801-specific IRQs
+ */
+#define IRQ_IXDP2801_RIV		IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2801_CNFG_MEDIA		IXP2000_BOARD_IRQ(27)
+#define IRQ_IXDP2801_CLOCK_REF		IXP2000_BOARD_IRQ(28)
+
+#define	IXDP2801_VALID_IRQ_MASK ( \
+		IXDP2X01_VALID_IRQ_MASK | \
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
+		IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
+
+#define	NR_IXDP2X01_IRQS		((IRQ_IXDP2801_CLOCK_REF) + 1)
+
+#endif /*_IRQS_H*/
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
new file mode 100644
index 00000000000..5df8479d948
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/ixdp2x00.h
+ *
+ * Register and other defines for IXDP2[48]00 platforms
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef _IXDP2X00_H_
+#define _IXDP2X00_H_
+
+/*
+ * On board CPLD memory map
+ */
+#define IXDP2X00_PHYS_CPLD_BASE		0xc7000000
+#define IXDP2X00_VIRT_CPLD_BASE		0xfe000000
+#define IXDP2X00_CPLD_SIZE		0x00100000
+
+
+#define IXDP2X00_CPLD_REG(x)  	\
+	(volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
+
+/*
+ * IXDP2400 CPLD registers
+ */
+#define IXDP2400_CPLD_SYSLED		IXDP2X00_CPLD_REG(0x0)  
+#define IXDP2400_CPLD_DISP_DATA		IXDP2X00_CPLD_REG(0x4)
+#define IXDP2400_CPLD_CLOCK_SPEED	IXDP2X00_CPLD_REG(0x8)
+#define IXDP2400_CPLD_INT_STAT		IXDP2X00_CPLD_REG(0xc)
+#define IXDP2400_CPLD_REV		IXDP2X00_CPLD_REG(0x10)
+#define IXDP2400_CPLD_SYS_CLK_M		IXDP2X00_CPLD_REG(0x14)
+#define IXDP2400_CPLD_SYS_CLK_N		IXDP2X00_CPLD_REG(0x18)
+#define IXDP2400_CPLD_INT_MASK		IXDP2X00_CPLD_REG(0x48)
+
+/*
+ * IXDP2800 CPLD registers
+ */
+#define IXDP2800_CPLD_INT_STAT		IXDP2X00_CPLD_REG(0x0)
+#define IXDP2800_CPLD_INT_MASK		IXDP2X00_CPLD_REG(0x140)
+
+
+#define	IXDP2X00_GPIO_I2C_ENABLE	0x02
+#define	IXDP2X00_GPIO_SCL		0x07
+#define	IXDP2X00_GPIO_SDA		0x06
+
+/*
+ * PCI devfns for on-board devices. We need these to be able to
+ * properly translate IRQs and for device removal.
+ */
+#define	IXDP2400_SLAVE_ENET_DEVFN	0x18	/* Bus 1 */
+#define	IXDP2400_MASTER_ENET_DEVFN	0x20	/* Bus 1 */
+#define	IXDP2400_MEDIA_DEVFN		0x28	/* Bus 1 */
+#define	IXDP2400_SWITCH_FABRIC_DEVFN	0x30	/* Bus 1 */
+
+#define	IXDP2800_SLAVE_ENET_DEVFN	0x20	/* Bus 1 */
+#define	IXDP2800_MASTER_ENET_DEVFN	0x18	/* Bus 1 */
+#define	IXDP2800_SWITCH_FABRIC_DEVFN	0x30	/* Bus 1 */
+
+#define	IXDP2X00_P2P_DEVFN		0x20	/* Bus 0 */
+#define	IXDP2X00_21555_DEVFN		0x30	/* Bus 0 */
+#define IXDP2X00_SLAVE_NPU_DEVFN	0x28	/* Bus 1 */
+#define	IXDP2X00_PMC_DEVFN		0x38	/* Bus 1 */
+#define IXDP2X00_MASTER_NPU_DEVFN	0x38	/* Bus 1 */
+
+#ifndef __ASSEMBLY__
+/*
+ * The master NPU is always PCI master.
+ */
+static inline unsigned int ixdp2x00_master_npu(void)
+{
+	return !!ixp2000_is_pcimaster();
+}
+
+/*
+ * Helper functions used by ixdp2400 and ixdp2800 specific code
+ */
+void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
+void ixdp2x00_slave_pci_postinit(void);
+void ixdp2x00_init_machine(void);
+void ixdp2x00_map_io(void);
+
+#endif
+
+#endif /*_IXDP2X00_H_ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
new file mode 100644
index 00000000000..4c1f04083e5
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h
+ *
+ * Platform definitions for IXDP2X01 && IXDP2801 systems
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista Software, Inc. 
+ *
+ * Based on original code Copyright (c) 2002-2003 Intel Corporation
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __IXDP2X01_H__
+#define __IXDP2X01_H__
+
+#define	IXDP2X01_PHYS_CPLD_BASE		0xc6024000
+#define	IXDP2X01_VIRT_CPLD_BASE		0xfe000000
+#define	IXDP2X01_CPLD_REGION_SIZE	0x00100000
+
+#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
+#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg)
+
+#define IXDP2X01_UART1_VIRT_BASE	IXDP2X01_CPLD_VIRT_REG(0x40)
+#define IXDP2X01_UART1_PHYS_BASE	IXDP2X01_CPLD_PHYS_REG(0x40)
+
+#define IXDP2X01_UART2_VIRT_BASE	IXDP2X01_CPLD_VIRT_REG(0x60)
+#define IXDP2X01_UART2_PHYS_BASE	IXDP2X01_CPLD_PHYS_REG(0x60)
+
+#define IXDP2X01_CS8900_VIRT_BASE	IXDP2X01_CPLD_VIRT_REG(0x80)
+#define IXDP2X01_CS8900_VIRT_END	(IXDP2X01_CS8900_VIRT_BASE + 16)
+
+#define IXDP2X01_CPLD_RESET_REG         IXDP2X01_CPLD_VIRT_REG(0x00)
+#define IXDP2X01_INT_MASK_SET_REG	IXDP2X01_CPLD_VIRT_REG(0x08)
+#define IXDP2X01_INT_STAT_REG		IXDP2X01_CPLD_VIRT_REG(0x0C)
+#define IXDP2X01_INT_RAW_REG		IXDP2X01_CPLD_VIRT_REG(0x10) 
+#define IXDP2X01_INT_MASK_CLR_REG	IXDP2X01_INT_RAW_REG
+#define IXDP2X01_INT_SIM_REG		IXDP2X01_CPLD_VIRT_REG(0x14)
+
+#define IXDP2X01_CPLD_FLASH_REG		IXDP2X01_CPLD_VIRT_REG(0x20)
+
+#define IXDP2X01_CPLD_FLASH_INTERN 	0x8000
+#define IXDP2X01_CPLD_FLASH_BANK_MASK 	0xF
+#define IXDP2X01_FLASH_WINDOW_BITS 	25
+#define IXDP2X01_FLASH_WINDOW_SIZE 	(1 << IXDP2X01_FLASH_WINDOW_BITS)
+#define IXDP2X01_FLASH_WINDOW_MASK 	(IXDP2X01_FLASH_WINDOW_SIZE - 1)
+
+#define	IXDP2X01_UART_CLK		1843200
+
+#define	IXDP2X01_GPIO_I2C_ENABLE	0x02
+#define	IXDP2X01_GPIO_SCL		0x07
+#define	IXDP2X01_GPIO_SDA		0x06
+
+#endif /* __IXDP2x01_H__ */
diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
new file mode 100644
index 00000000000..19d80379a3e
--- /dev/null
+++ b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
@@ -0,0 +1,457 @@
+/*
+ * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h
+ *
+ * Chipset register definitions for IXP2400/2800 based systems.
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ *
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef _IXP2000_REGS_H_
+#define _IXP2000_REGS_H_
+
+/*
+ * IXP2000 linux memory map:
+ *
+ * virt		phys		size
+ * fb000000	db000000	16M		PCI CFG1
+ * fc000000	da000000	16M		PCI CFG0
+ * fd000000	d8000000	16M		PCI I/O
+ * fe[0-7]00000			8M		per-platform mappings
+ * fe900000	80000000	1M		SRAM #0 (first MB)
+ * fea00000	cb400000	1M		SCRATCH ring get/put
+ * feb00000	c8000000	1M		MSF
+ * fec00000	df000000	1M		PCI CSRs
+ * fed00000	de000000	1M		PCI CREG
+ * fee00000	d6000000	1M		INTCTL
+ * fef00000	c0000000	1M		CAP
+ */
+
+/* 
+ * Static I/O regions.
+ *
+ * Most of the registers are clumped in 4K regions spread throughout
+ * the 0xc0000000 -> 0xc0100000 address range, but we just map in
+ * the whole range using a single 1 MB section instead of small