diff options
author | James Morris <jmorris@namei.org> | 2008-08-28 10:47:34 +1000 |
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committer | James Morris <jmorris@namei.org> | 2008-08-28 10:47:34 +1000 |
commit | 86d688984deefa3ae5a802880c11f2b408b5d6cf (patch) | |
tree | 7ea5e8189b0a774626d3ed7c3c87df2495a4c4a0 /arch/arm/mach-ixp2000/include/mach/system.h | |
parent | 93c06cbbf9fea5d5be1778febb7fa9ab1a74e5f5 (diff) | |
parent | 4c246edd2550304df5b766cc841584b2bb058843 (diff) |
Merge branch 'master' into next
Diffstat (limited to 'arch/arm/mach-ixp2000/include/mach/system.h')
-rw-r--r-- | arch/arm/mach-ixp2000/include/mach/system.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h new file mode 100644 index 00000000000..2e9c68f95a2 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/system.h @@ -0,0 +1,49 @@ +/* + * arch/arm/mach-ixp2000/include/mach/system.h + * + * Copyright (C) 2002 Intel Corp. + * Copyricht (C) 2003-2005 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <mach/hardware.h> +#include <asm/mach-types.h> + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode) +{ + local_irq_disable(); + + /* + * Reset flash banking register so that we are pointing at + * RedBoot bank. + */ + if (machine_is_ixdp2401()) { + ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, + ((0 >> IXDP2X01_FLASH_WINDOW_BITS) + | IXDP2X01_CPLD_FLASH_INTERN)); + ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff); + } + + /* + * On IXDP2801 we need to write this magic sequence to the CPLD + * to cause a complete reset of the CPU and all external devices + * and move the flash bank register back to 0. + */ + if (machine_is_ixdp2801() || machine_is_ixdp28x5()) { + unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG; + + reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF); + ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg); + ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000); + } + + ixp2000_reg_wrb(IXP2000_RESET0, RSTALL); +} |