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authorArnd Bergmann <arnd@arndb.de>2012-01-09 16:01:00 +0000
committerArnd Bergmann <arnd@arndb.de>2012-01-09 16:01:00 +0000
commita07613a54d700a974f3a4a657da78ef5d097315d (patch)
treee4bc91713e02fa6d8f08b07de53ea8f905593dfa /arch/arm/mach-imx/src.c
parent65db039bf7402f0a5b19cbf6dcff55ebea433b8b (diff)
parent928a11ba36f999436915ea2b1eadf54301f93059 (diff)
Merge branch 'samsung/dt' into samsung/cleanup
Conflicts: arch/arm/mach-s3c64xx/Makefile arch/arm/mach-s5pc100/Makefile arch/arm/mach-s5pv210/Makefile Pull in previously resolved conflicts: The Makefiles were reorganized in the "rmk/restart" series and modified in the "samsung/cleanup series". This also pulls in the other conflict resolutions from the restart series against the samsung/dt series. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/src.c')
-rw-r--r--arch/arm/mach-imx/src.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index a8e33681b73..4bde04f99e3 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -19,6 +19,7 @@
#define SRC_SCR 0x000
#define SRC_GPR1 0x020
+#define BP_SRC_SCR_WARM_RESET_ENABLE 0
#define BP_SRC_SCR_CORE1_RST 14
#define BP_SRC_SCR_CORE1_ENABLE 22
@@ -46,11 +47,33 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
src_base + SRC_GPR1 + cpu * 8);
}
+void imx_src_prepare_restart(void)
+{
+ u32 val;
+
+ /* clear enable bits of secondary cores */
+ val = readl_relaxed(src_base + SRC_SCR);
+ val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
+ writel_relaxed(val, src_base + SRC_SCR);
+
+ /* clear persistent entry register of primary core */
+ writel_relaxed(0, src_base + SRC_GPR1);
+}
+
void __init imx_src_init(void)
{
struct device_node *np;
+ u32 val;
np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
src_base = of_iomap(np, 0);
WARN_ON(!src_base);
+
+ /*
+ * force warm reset sources to generate cold reset
+ * for a more reliable restart
+ */
+ val = readl_relaxed(src_base + SRC_SCR);
+ val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
+ writel_relaxed(val, src_base + SRC_SCR);
}