diff options
| author | Dirk Behme <dirk.behme@de.bosch.com> | 2013-04-26 10:13:56 +0200 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-06-17 15:45:09 +0800 |
| commit | b3a9c315378ff811bf34393f2f0a6e8b9ffced3b (patch) | |
| tree | efb7315aba99bd79aecf017f1e6786b9415e1480 /arch/arm/mach-imx/clk-imx6q.c | |
| parent | 75f83d06c3305e0f0a00e7d141acf8ceef608fe9 (diff) | |
ARM: i.MX6: add i.MX6 specific L2 cache configuration
To improve the performance and power consumption add an i.MX6
specific L2 cache initialization.
This configuration is taken from Freescale's kernel patch
"ENGR00153601 [MX6]Adjust L2 cache parameter" [1]
with two additional improvements:
a) The L2X0_POWER_CTRL has only the two bits we set. So no need
to read the register before. Remove the register read done
in Freescale's patch.
b) In the L2X0_PREFETCH_CTRL register, besides the double linefill (bit[30]),
additionally enable the instruction and data prefetch (bit[29-28]).
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
[1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6q.c')
0 files changed, 0 insertions, 0 deletions