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authorOlof Johansson <olof@lixom.net>2012-10-01 14:15:02 -0700
committerOlof Johansson <olof@lixom.net>2012-10-01 14:15:02 -0700
commited0a0ed0a4e0e6eeebfa154f97ebb41abc5bbee8 (patch)
tree3ca115b6580b70b20d21da179f004b14f54edc8e /arch/arm/mach-exynos
parent17a505edb09495510ac8998450980472c412455b (diff)
parent9cf1c871526cf6bfec2a653e1e068ee72592542c (diff)
Merge branch 'next/cleanup' into HEAD
Conflicts: drivers/staging/tidspbridge/core/wdt.c drivers/usb/host/Kconfig drivers/w1/masters/omap_hdq.c
Diffstat (limited to 'arch/arm/mach-exynos')
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c9
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h1
2 files changed, 0 insertions, 10 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c6706..3b00e299b62 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
}
-static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
-{
- return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
-}
-
static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -672,10 +667,6 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
- .name = "gps",
- .enable = exynos5_clk_ip_gps_ctrl,
- .ctrlbit = ((1 << 3) | (1 << 2) | (1 << 0)),
- }, {
.name = "nfcon",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 22),
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c941053dd5a..6d33f50c2e5 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -131,7 +131,6 @@
#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
-#define EXYNOS5_PA_SYSMMU_GPS 0x12630000
#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000