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| author | Nicolas Ferre <nicolas.ferre@atmel.com> | 2010-10-22 18:55:39 +0200 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2010-10-26 11:32:48 +0200 |
| commit | a2a571b74a3881963d8d09deb272d13afe5b49e3 (patch) | |
| tree | 491cf5ff56293287906f9cfec785345f24cd2180 /arch/arm/mach-at91/pm.c | |
| parent | 8aeeda822fbfe7da2d4ea391a9757e9532796598 (diff) | |
AT91: pm: make sure that r0 is 0 when dealing with cache operations
When using CP15 cache operations (c7), we make sure that Rd (r0)
is actually 0 as ARM 926 TRM is saying.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/pm.c')
| -rw-r--r-- | arch/arm/mach-at91/pm.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 87a31baf1cb..dafbacc25eb 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -261,8 +261,13 @@ static int at91_pm_enter(suspend_state_t state) * For ARM 926 based chips, this requirement is weaker * as at91sam9 can access a RAM in self-refresh mode. */ - asm("b 1f; .align 5; 1:"); - asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ + asm volatile ( "mov r0, #0\n\t" + "b 1f\n\t" + ".align 5\n\t" + "1: mcr p15, 0, r0, c7, c10, 4\n\t" + : /* no output */ + : /* no input */ + : "r0"); saved_lpr = sdram_selfrefresh_enable(); wait_for_interrupt_enable(); sdram_selfrefresh_disable(saved_lpr); |