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authorTakashi Iwai <tiwai@suse.de>2010-02-17 14:24:46 +0100
committerTakashi Iwai <tiwai@suse.de>2010-02-17 14:24:46 +0100
commit7fb3a069bc5d3577409c2ae89f89cd264ff85816 (patch)
tree7fe3ba3b95faeecb01e4feafb9288ef4b523c6b3 /arch/arm/include/asm/cacheflush.h
parent291186e049d7f8178ad31d43c38a53889f25d79e (diff)
parent9d3415a8cc76ff65c6602a121ac318432c5cd7ba (diff)
Merge branch 'fix/misc' into topic/misc
Conflicts: sound/pci/hda/patch_realtek.c
Diffstat (limited to 'arch/arm/include/asm/cacheflush.h')
-rw-r--r--arch/arm/include/asm/cacheflush.h20
1 files changed, 17 insertions, 3 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 730aefcfbee..c77d2fa1f6e 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -154,16 +154,16 @@
* Please note that the implementation of these, and the required
* effects are cache-type (VIVT/VIPT/PIPT) specific.
*
- * flush_cache_kern_all()
+ * flush_kern_all()
*
* Unconditionally clean and invalidate the entire cache.
*
- * flush_cache_user_mm(mm)
+ * flush_user_all()
*
* Clean and invalidate all user space cache entries
* before a change of page tables.
*
- * flush_cache_user_range(start, end, flags)
+ * flush_user_range(start, end, flags)
*
* Clean and invalidate a range of cache entries in the
* specified address space before a change of page tables.
@@ -179,6 +179,20 @@
* - start - virtual start address
* - end - virtual end address
*
+ * coherent_user_range(start, end)
+ *
+ * Ensure coherency between the Icache and the Dcache in the
+ * region described by start, end. If you have non-snooping
+ * Harvard caches, you need to implement this function.
+ * - start - virtual start address
+ * - end - virtual end address
+ *
+ * flush_kern_dcache_area(kaddr, size)
+ *
+ * Ensure that the data held in page is written back.
+ * - kaddr - page address
+ * - size - region size
+ *
* DMA Cache Coherency
* ===================
*