diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-05-14 15:33:42 +0200 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2012-05-14 15:33:42 +0200 |
commit | d2819f80d465672b09c2f4cb52303b7f951c4d0f (patch) | |
tree | aa0262703e86b97ad1460c722e78d7233e24e3bb /arch/arm/boot/dts/spear3xx.dtsi | |
parent | 5df33a62c4a028d6fc7f2dcc159827d09b7334b8 (diff) | |
parent | 366695ff706669d40459174b1cbb78fca42f4e06 (diff) |
Merge branch 'spear/pinctrl' into spear/clock
Conflicts:
arch/arm/mach-spear3xx/Makefile
arch/arm/mach-spear3xx/clock.c
arch/arm/mach-spear3xx/include/mach/generic.h
arch/arm/mach-spear6xx/clock.c
arch/arm/plat-spear/Makefile
drivers/pinctrl/core.c
This resolves some annoying merge conflicts.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/spear3xx.dtsi')
-rw-r--r-- | arch/arm/boot/dts/spear3xx.dtsi | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi new file mode 100644 index 00000000000..0ae7c8e8631 --- /dev/null +++ b/arch/arm/boot/dts/spear3xx.dtsi @@ -0,0 +1,144 @@ +/* + * DTS file for all SPEAr3xx SoCs + * + * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&vic>; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + vic: interrupt-controller@f1100000 { + compatible = "arm,pl190-vic"; + interrupt-controller; + reg = <0xf1100000 0x1000>; + #interrupt-cells = <1>; + }; + + dma@fc400000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0xfc400000 0x1000>; + interrupt-parent = <&vic>; + interrupts = <8>; + status = "disabled"; + }; + + gmac: eth@e0800000 { + compatible = "st,spear600-gmac"; + reg = <0xe0800000 0x8000>; + interrupts = <23 22>; + interrupt-names = "macirq", "eth_wake_irq"; + status = "disabled"; + }; + + smi: flash@fc000000 { + compatible = "st,spear600-smi"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xfc000000 0x1000>; + interrupts = <9>; + status = "disabled"; + }; + + spi0: spi@d0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xd0100000 0x1000>; + interrupts = <20>; + status = "disabled"; + }; + + ehci@e1800000 { + compatible = "st,spear600-ehci", "usb-ehci"; + reg = <0xe1800000 0x1000>; + interrupts = <26>; + status = "disabled"; + }; + + ohci@e1900000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe1900000 0x1000>; + interrupts = <25>; + status = "disabled"; + }; + + ohci@e2100000 { + compatible = "st,spear600-ohci", "usb-ohci"; + reg = <0xe2100000 0x1000>; + interrupts = <27>; + status = "disabled"; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0xd0000000 0xd0000000 0x30000000>; + + gpio0: gpio@fc980000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xfc980000 0x1000>; + interrupts = <11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + i2c0: i2c@d0180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xd0180000 0x1000>; + interrupts = <21>; + status = "disabled"; + }; + + rtc@fc900000 { + compatible = "st,spear-rtc"; + reg = <0xfc900000 0x1000>; + interrupts = <10>; + status = "disabled"; + }; + + serial@d0000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xd0000000 0x1000>; + interrupts = <19>; + status = "disabled"; + }; + + wdt@fc880000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0xfc880000 0x1000>; + interrupts = <12>; + status = "disabled"; + }; + }; + }; +}; |