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authorPhilipp Zabel <p.zabel@pengutronix.de>2013-07-24 18:35:28 +0200
committerShawn Guo <shawn.guo@linaro.org>2013-08-22 23:29:48 +0800
commit9273ee3528596f6d4f67244f3532da39de0e34af (patch)
treea31167649486b8c94af02cf8d9ef330b9d25bee5 /arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
parent38501179c932245bc02a0becbd7dd5f6677902e3 (diff)
ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index c6fff174dfd..a4194f2c7d8 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -20,6 +20,20 @@
};
};
+&ecspi3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3_1>;
+ status = "okay";
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio4 24 0>;
+
+ flash@0 {
+ compatible = "m25p80";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
@@ -28,6 +42,7 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
>;
};
};