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authorKristen Carlson Accardi <kristen.c.accardi@intel.com>2006-07-12 08:59:00 -0700
committerGreg Kroah-Hartman <gregkh@suse.de>2006-07-12 16:05:48 -0700
commitffadcc2ff42ecedf71ea67d9051ff028927aed08 (patch)
tree540351be72173f69c552c05dfeffd0804ca0bd6b /Documentation
parent6f0312fd7e0e6f96fd847b0b2e1e0d2d2e8ef89d (diff)
[PATCH] PCI: PCIE power management quirk
When changing power states from D0->DX and then from DX->D0, some Intel PCIE chipsets will cause a device reset to occur. This will cause problems for any D State other than D3, since any state information that the driver will expect to be present coming from a D1 or D2 state will have been cleared. This patch addes a flag to the pci_dev structure to indicate that devices should not use states D1 or D2, and will set that flag for the affected chipsets. This patch also modifies pci_set_power_state() so that when a device driver tries to set the power state on a device that is downstream from an affected chipset, or on one of the affected devices it only allows state changes to or from D0 & D3. In addition, this patch allows the delay time between D3->D0 to be changed via a quirk. These chipsets also need additional time to change states beyond the normal 10ms. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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