diff options
| author | Alex Chiang <achiang@hp.com> | 2009-10-21 21:45:15 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-10-30 14:59:52 -0700 |
| commit | 468727ab1273a0f95562befa611a3ce39778599c (patch) | |
| tree | 6b67734fda2bc426ab5586e2e7a0a8c400e4ff56 /Documentation/ABI/testing/sysfs-devices-system-cpu | |
| parent | 1a6f2a7512021ceae3c4201c7aab07f032e9ce91 (diff) | |
Documentation: ABI: rename sysfs-devices-cache_disable properly
Rename sysfs-devices-cache_disable to sysfs-devices-system-cpu, in
order to keep a stricter correlation between a sysfs directory and
its documentation.
Reported-by: David Rientjes <rientjes@google.com>
Signed-off-by: Alex Chiang <achiang@hp.com>
Acked-by: David Rientjes <rientjes@google.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'Documentation/ABI/testing/sysfs-devices-system-cpu')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-devices-system-cpu | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu new file mode 100644 index 00000000000..175bb4f7051 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -0,0 +1,18 @@ +What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X +Date: August 2008 +KernelVersion: 2.6.27 +Contact: mark.langsdorf@amd.com +Description: These files exist in every cpu's cache index directories. + There are currently 2 cache_disable_# files in each + directory. Reading from these files on a supported + processor will return that cache disable index value + for that processor and node. Writing to one of these + files will cause the specificed cache index to be disabled. + + Currently, only AMD Family 10h Processors support cache index + disable, and only for their L3 caches. See the BIOS and + Kernel Developer's Guide at + http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf + for formatting information and other details on the + cache index disable. +Users: joachim.deguara@amd.com |