diff options
author | Dan Williams <dan.j.williams@intel.com> | 2009-03-25 09:13:25 -0700 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2009-03-25 09:13:25 -0700 |
commit | 06164f3194e01ea4c76941ac60f541d656c8975f (patch) | |
tree | 0a5edc96e053ce0cf90139b48bc2ca7c7c130186 | |
parent | 54aee6a5f560d0e1bf3f39987c6ebe06daeb0ce1 (diff) |
async_tx: provide __async_inline for HAS_DMA=n archs
To allow an async_tx routine to be compiled away on HAS_DMA=n arch it
needs to be declared __always_inline otherwise the compiler may emit
code and cause a link error.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
-rw-r--r-- | crypto/async_tx/async_xor.c | 7 | ||||
-rw-r--r-- | include/linux/async_tx.h | 9 |
2 files changed, 11 insertions, 5 deletions
diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index 595b78672b3..95fe2c8d6c5 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -30,11 +30,8 @@ #include <linux/raid/xor.h> #include <linux/async_tx.h> -/* do_async_xor - dma map the pages and perform the xor with an engine. - * This routine is marked __always_inline so it can be compiled away - * when CONFIG_DMA_ENGINE=n - */ -static __always_inline struct dma_async_tx_descriptor * +/* do_async_xor - dma map the pages and perform the xor with an engine */ +static __async_inline struct dma_async_tx_descriptor * do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list, unsigned int offset, int src_cnt, size_t len, enum async_tx_flags flags, diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h index 45f6297821b..5fc2ef8d97f 100644 --- a/include/linux/async_tx.h +++ b/include/linux/async_tx.h @@ -21,6 +21,15 @@ #include <linux/spinlock.h> #include <linux/interrupt.h> +/* on architectures without dma-mapping capabilities we need to ensure + * that the asynchronous path compiles away + */ +#ifdef CONFIG_HAS_DMA +#define __async_inline +#else +#define __async_inline __always_inline +#endif + /** * dma_chan_ref - object used to manage dma channels received from the * dmaengine core. |