diff options
| author | Robert P. J. Day <rpjday@mindspring.com> | 2007-05-08 00:37:51 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-05-08 11:15:27 -0700 |
| commit | 538c79248c0dc1a4a37d92254a571bd62f6eb7f2 (patch) | |
| tree | 337ef2dae486a1ecf8cab8a0fc4e63f068ce404b | |
| parent | 28b230ed71df88a3b2df58e3f177c3c7be1753b9 (diff) | |
remove unused header file: drivers/video/riva/nv4ref.h
Signed-off-by: Robert P. J. Day <rpjday@mindspring.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| -rw-r--r-- | drivers/video/riva/nv4ref.h | 2445 |
1 files changed, 0 insertions, 2445 deletions
diff --git a/drivers/video/riva/nv4ref.h b/drivers/video/riva/nv4ref.h deleted file mode 100644 index 3b5f9117c37..00000000000 --- a/drivers/video/riva/nv4ref.h +++ /dev/null @@ -1,2445 +0,0 @@ - /***************************************************************************\ -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NOTICE TO USER: The source code is copyrighted under U.S. and *| -|* international laws. Users and possessors of this source code are *| -|* hereby granted a nonexclusive, royalty-free copyright license to *| -|* use this code in individual and commercial software. *| -|* *| -|* Any use of this source code must include, in the user documenta- *| -|* tion and internal comments to the code, notices to the end user *| -|* as follows: *| -|* *| -|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| -|* *| -|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| -|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| -|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| -|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| -|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| -|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| -|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| -|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| -|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| -|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| -|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| -|* *| -|* U.S. Government End Users. This source code is a "commercial *| -|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| -|* consisting of "commercial computer software" and "commercial *| -|* computer software documentation," as such terms are used in *| -|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| -|* ment only as a commercial end item. Consistent with 48 C.F.R. *| -|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| -|* all U.S. Government End Users acquire the source code with only *| -|* those rights set forth herein. *| -|* *| - \***************************************************************************/ - -/* - * GPL licensing note -- nVidia is allowing a liberal interpretation of - * the documentation restriction above, to merely say that this nVidia's - * copyright and disclaimer should be included with all code derived - * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 - */ - - /***************************************************************************\ -|* Modified 1999 by Fredrik Reite (fredrik@reite.com) *| - \***************************************************************************/ - - -#ifndef __NV4REF_H__ -#define __NV4REF_H__ - -/* Magic values to lock/unlock extended regs */ -#define NV_CIO_SR_LOCK_INDEX 0x0000001F /* */ -#define NV_CIO_SR_UNLOCK_RW_VALUE 0x00000057 /* */ -#define NV_CIO_SR_UNLOCK_RO_VALUE 0x00000075 /* */ -#define NV_CIO_SR_LOCK_VALUE 0x00000099 /* */ - -#define UNLOCK_EXT_MAGIC 0x57 -#define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */ - -#define LOCK_EXT_INDEX 0x6 - -#define NV_PCRTC_HORIZ_TOTAL 0x00 -#define NV_PCRTC_HORIZ_DISPLAY_END 0x01 -#define NV_PCRTC_HORIZ_BLANK_START 0x02 - -#define NV_PCRTC_HORIZ_BLANK_END 0x03 -#define NV_PCRTC_HORIZ_BLANK_END_EVRA 7:7 -#define NV_PCRTC_HORIZ_BLANK_END_DISPLAY_END_SKEW 6:5 -#define NV_PCRTC_HORIZ_BLANK_END_HORIZ_BLANK_END 4:0 - -#define NV_PCRTC_HORIZ_RETRACE_START 0x04 - -#define NV_PCRTC_HORIZ_RETRACE_END 0x05 -#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_BLANK_END_5 7:7 -#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_SKEW 6:5 -#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_END 4:0 - -#define NV_PCRTC_VERT_TOTAL 0x06 - -#define NV_PCRTC_OVERFLOW 0x07 -#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_9 7:7 -#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_9 6:6 -#define NV_PCRTC_OVERFLOW_VERT_TOTAL_9 5:5 -#define NV_PCRTC_OVERFLOW_LINE_COMPARE_8 4:4 -#define NV_PCRTC_OVERFLOW_VERT_BLANK_START_8 3:3 -#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_8 2:2 -#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_8 1:1 -#define NV_PCRTC_OVERFLOW_VERT_TOTAL_8 0:0 - -#define NV_PCRTC_PRESET_ROW_SCAN 0x08 - -#define NV_PCRTC_MAX_SCAN_LINE 0x09 -#define NV_PCRTC_MAX_SCAN_LINE_DOUBLE_SCAN 7:7 -#define NV_PCRTC_MAX_SCAN_LINE_LINE_COMPARE_9 6:6 -#define NV_PCRTC_MAX_SCAN_LINE_VERT_BLANK_START_9 5:5 -#define NV_PCRTC_MAX_SCAN_LINE_MAX_SCAN_LINE 4:0 - -#define NV_PCRTC_CURSOR_START 0x0A -#define NV_PCRTC_CURSOR_END 0x0B -#define NV_PCRTC_START_ADDR_HIGH 0x0C -#define NV_PCRTC_START_ADDR_LOW 0x0D -#define NV_PCRTC_CURSOR_LOCATION_HIGH 0x0E -#define NV_PCRTC_CURSOR_LOCATION_LOW 0x0F - -#define NV_PCRTC_VERT_RETRACE_START 0x10 -#define NV_PCRTC_VERT_RETRACE_END 0x11 -#define NV_PCRTC_VERT_DISPLAY_END 0x12 -#define NV_PCRTC_OFFSET 0x13 -#define NV_PCRTC_UNDERLINE_LOCATION 0x14 -#define NV_PCRTC_VERT_BLANK_START 0x15 -#define NV_PCRTC_VERT_BLANK_END 0x16 -#define NV_PCRTC_MODE_CONTROL 0x17 -#define NV_PCRTC_LINE_COMPARE 0x18 - -/* Extended offset and start address */ -#define NV_PCRTC_REPAINT0 0x19 -#define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5 -#define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0 - -/* Horizonal extended bits */ -#define NV_PCRTC_HORIZ_EXTRA 0x2d -#define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4 -#define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3 -#define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2 -#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1 -#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0 - -/* Assorted extra bits */ -#define NV_PCRTC_EXTRA 0x25 -#define NV_PCRTC_EXTRA_OFFSET_11 5:5 -#define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4 -#define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3 -#define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2 -#define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1 -#define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0 - -/* Controls how much data the refresh fifo requests */ -#define NV_PCRTC_FIFO_CONTROL 0x1b -#define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3 -#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4 - -/* When the fifo occupancy falls below *twice* the watermark, - * the refresh fifo will start to be refilled. If this value is - * too low, you will get junk on the screen. Too high, and performance - * will suffer. Watermark in units of 8 bytes - */ -#define NV_PCRTC_FIFO 0x20 -#define NV_PCRTC_FIFO_RESET 7:7 -#define NV_PCRTC_FIFO_WATERMARK 5:0 - -/* Various flags */ -#define NV_PCRTC_REPAINT1 0x1a -#define NV_PCRTC_REPAINT1_HSYNC 7:7 -#define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01 -#define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00 -#define NV_PCRTC_REPAINT1_VSYNC 6:6 -#define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01 -#define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00 -#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4 -#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01 -#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00 -#define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2 -#define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01 -#define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */ -#define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1 -#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00 -#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01 - -#define NV_PCRTC_GRCURSOR0 0x30 -#define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0 - -#define NV_PCRTC_GRCURSOR1 0x31 -#define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3 -#define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1 -#define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0 -#define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1 -#define NV_PCRTC_GRCURSOR1_CURSOR 0:0 -#define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0 -#define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1 - -/* Controls what the format of the framebuffer is */ -#define NV_PCRTC_PIXEL 0x28 -#define NV_PCRTC_PIXEL_MODE 7:7 -#define NV_PCRTC_PIXEL_MODE_TV 0x01 -#define NV_PCRTC_PIXEL_MODE_VGA 0x00 -#define NV_PCRTC_PIXEL_TV_MODE 6:6 -#define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00 -#define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01 -#define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3 -#define NV_PCRTC_PIXEL_FORMAT 1:0 -#define NV_PCRTC_PIXEL_FORMAT_VGA 0x00 -#define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01 -#define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02 -#define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03 - -/* RAMDAC registers and fields */ -#define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */ -#define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */ -#define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */ -#define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */ -#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 /* RW-4R */ -#define NV_PRAMDAC_NVPLL_COEFF_MDIV 7:0 /* RWIUF */ -#define NV_PRAMDAC_NVPLL_COEFF_NDIV 15:8 /* RWIUF */ -#define NV_PRAMDAC_NVPLL_COEFF_PDIV 18:16 /* RWIVF */ -#define NV_PRAMDAC_MPLL_COEFF 0x00680504 /* RW-4R */ -#define NV_PRAMDAC_MPLL_COEFF_MDIV 7:0 /* RWIUF */ -#define NV_PRAMDAC_MPLL_COEFF_NDIV 15:8 /* RWIUF */ -#define NV_PRAMDAC_MPLL_COEFF_PDIV 18:16 /* RWIVF */ -#define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */ -#define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */ -#define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */ -#define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */ -#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */ -#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */ -#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */ -#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */ - -/* Master Control */ -#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */ -#define NV_PMC_BOOT_0 0x00000000 /* R--4R */ -#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* C--VF */ -#define NV_PMC_BOOT_0_MINOR_REVISION_0 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* C--VF */ -#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_IMPLEMENTATION 11:8 /* C--VF */ -#define NV_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_ARCHITECTURE 15:12 /* C--VF */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV0 0x00000000 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV1 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV2 0x00000002 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV3 0x00000003 /* ----V */ -#define NV_PMC_BOOT_0_ARCHITECTURE_NV4 0x00000004 /* C---V */ -#define NV_PMC_BOOT_0_FIB_REVISION 19:16 /* C--VF */ -#define NV_PMC_BOOT_0_FIB_REVISION_0 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MASK_REVISION 23:20 /* C--VF */ -#define NV_PMC_BOOT_0_MASK_REVISION_A 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_MASK_REVISION_B 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_MANUFACTURER 27:24 /* C--UF */ -#define NV_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x00000000 /* C---V */ -#define NV_PMC_BOOT_0_FOUNDRY 31:28 /* C--VF */ -#define NV_PMC_BOOT_0_FOUNDRY_SGS 0x00000000 /* ----V */ -#define NV_PMC_BOOT_0_FOUNDRY_HELIOS 0x00000001 /* ----V */ -#define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000002 /* C---V */ -#define NV_PMC_INTR_0 0x00000100 /* RW-4R */ -#define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */ -#define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */ -#define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PGRAPH 12:12 /* R--VF */ -#define NV_PMC_INTR_0_PGRAPH_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PGRAPH_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */ -#define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */ -#define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PCRTC 24:24 /* R--VF */ -#define NV_PMC_INTR_0_PCRTC_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PCRTC_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */ -#define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */ -#define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */ -#define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */ -#define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */ -#define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */ -#define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */ -#define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */ -#define NV_PMC_INTR_READ_0 0x00000160 /* R--4R */ -#define NV_PMC_INTR_READ_0_INTA 0:0 /* R--VF */ -#define NV_PMC_INTR_READ_0_INTA_LOW 0x00000000 /* R---V */ -#define NV_PMC_INTR_READ_0_INTA_HIGH 0x00000001 /* R---V */ -#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ -#define NV_PMC_ENABLE_PMEDIA 4:4 /* RWIVF */ -#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ -#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */ -#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PPMI 16:16 /* RWIVF */ -#define NV_PMC_ENABLE_PPMI_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PPMI_ENABLED 0x00000001 /* RW--V */ -#define NV_PMC_ENABLE_PFB 20:20 /* RWIVF */ -#define NV_PMC_ENABLE_PFB_DISABLED 0x00000000 /* RW--V */ -#define NV_PMC_ENABLE_PFB_ENABLED 0x00000001 /* RWI-V */ -#define NV_PMC_ENABLE_PCRTC 24:24 /* RWIVF */ -#define NV_PMC_ENABLE_PCRTC_DISABLED 0x00000000 /* RW--V */ -#define NV_PMC_ENABLE_PCRTC_ENABLED 0x00000001 /* RWI-V */ -#define NV_PMC_ENABLE_PVIDEO 28:28 /* RWIVF */ -#define NV_PMC_ENABLE_PVIDEO_DISABLED 0x00000000 /* RWI-V */ -#define NV_PMC_ENABLE_PVIDEO_ENABLED 0x00000001 /* RW--V */ - -/* dev_timer.ref */ -#define NV_PTIMER 0x00009FFF:0x00009000 /* RW--D */ -#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */ -#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */ -#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */ -#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */ -#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */ -#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */ -#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */ -#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */ -#define NV_PTIMER_NUMERATOR 0x00009200 /* RW-4R */ -#define NV_PTIMER_NUMERATOR_VALUE 15:0 /* RWIUF */ -#define NV_PTIMER_NUMERATOR_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PTIMER_DENOMINATOR 0x00009210 /* RW-4R */ -#define NV_PTIMER_DENOMINATOR_VALUE 15:0 /* RWIUF */ -#define NV_PTIMER_DENOMINATOR_VALUE_0 0x00000000 /* RWI-V */ -#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */ -#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */ -#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */ -#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */ -#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */ -#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */ - -/* dev_fifo.ref */ -#define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */ -#define NV_PFIFO_DELAY_0 0x00002040 /* RW-4R */ -#define NV_PFIFO_DELAY_0_WAIT_RETRY 9:0 /* RWIUF */ -#define NV_PFIFO_DELAY_0_WAIT_RETRY_0 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_TIMESLICE 0x00002044 /* RW-4R */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT 16:0 /* RWIUF */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ -#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ -#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ -#define NV_PFIFO_PIO_TIMESLICE 0x00002048 /* RW-4R */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT 16:0 /* RWIUF */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ -#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ -#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ -#define NV_PFIFO_TIMESLICE 0x0000204C /* RW-4R */ -#define NV_PFIFO_TIMESLICE_TIMER 17:0 /* RWIUF */ -#define NV_PFIFO_TIMESLICE_TIMER_EXPIRED 0x0003FFFF /* RWI-V */ -#define NV_PFIFO_NEXT_CHANNEL 0x00002050 /* RW-4R */ -#define NV_PFIFO_NEXT_CHANNEL_CHID 3:0 /* RWXUF */ -#define NV_PFIFO_NEXT_CHANNEL_MODE 8:8 /* RWXVF */ -#define NV_PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 /* RW--V */ -#define NV_PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_NEXT_CHANNEL_SWITCH 12:12 /* RWIVF */ -#define NV_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DEBUG_0 0x00002080 /* R--4R */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR0 0:0 /* R-XVF */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR1 4:4 /* R-XVF */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */ -#define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */ -#define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */ -#define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */ -#define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_0_DMA_PT 16:16 /* RWXVF */ -#define NV_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x00000000 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PT_PENDING 0x00000001 /* R---V */ -#define NV_PFIFO_INTR_0_DMA_PT_RESET 0x00000001 /* -W--V */ -#define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */ -#define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_DMA_PUSHER 12:12 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_INTR_EN_0_DMA_PT 16:16 /* RWIVF */ -#define NV_PFIFO_INTR_EN_0_DMA_PT_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */ -#define NV_PFIFO_RAMHT_BASE_ADDRESS 8:4 /* RWIUF */ -#define NV_PFIFO_RAMHT_BASE_ADDRESS_10000 0x00000010 /* RWI-V */ -#define NV_PFIFO_RAMHT_SIZE 17:16 /* RWIUF */ -#define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */ -#define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */ -#define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */ -#define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */ -#define NV_PFIFO_RAMHT_SEARCH 25:24 /* RWIUF */ -#define NV_PFIFO_RAMHT_SEARCH_16 0x00000000 /* RWI-V */ -#define NV_PFIFO_RAMHT_SEARCH_32 0x00000001 /* RW--V */ -#define NV_PFIFO_RAMHT_SEARCH_64 0x00000002 /* RW--V */ -#define NV_PFIFO_RAMHT_SEARCH_128 0x00000003 /* RW--V */ -#define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */ -#define NV_PFIFO_RAMFC_BASE_ADDRESS 8:1 /* RWIUF */ -#define NV_PFIFO_RAMFC_BASE_ADDRESS_11000 0x00000088 /* RWI-V */ -#define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */ -#define NV_PFIFO_RAMRO_BASE_ADDRESS 8:1 /* RWIUF */ -#define NV_PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000089 /* RWI-V */ -#define NV_PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000090 /* RW--V */ -#define NV_PFIFO_RAMRO_SIZE 16:16 /* RWIVF */ -#define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */ -#define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHES 0x00002500 /* RW-4R */ -#define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */ -#define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */ -#define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */ -#define NV_PFIFO_CACHES_DMA_SUSPEND 4:4 /* R--VF */ -#define NV_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 /* R---V */ -#define NV_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000001 /* R---V */ -#define NV_PFIFO_MODE 0x00002504 /* RW-4R */ -#define NV_PFIFO_MODE_CHANNEL_0 0:0 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_0_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_0_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_1 1:1 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_1_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_1_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_2 2:2 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_2_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_2_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_3 3:3 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_3_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_3_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_4 4:4 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_4_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_4_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_5 5:5 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_5_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_5_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_6 6:6 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_6_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_6_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_7 7:7 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_7_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_7_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_8 8:8 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_8_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_8_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_9 9:9 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_9_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_9_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_10 10:10 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_10_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_10_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_11 11:11 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_11_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_11_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_12 12:12 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_12_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_12_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_13 13:13 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_13_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_13_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_14 14:14 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_14_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_14_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_MODE_CHANNEL_15 15:15 /* RWIVF */ -#define NV_PFIFO_MODE_CHANNEL_15_PIO 0x00000000 /* RWI-V */ -#define NV_PFIFO_MODE_CHANNEL_15_DMA 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA 0x00002508 /* RW-4R */ -#define NV_PFIFO_DMA_CHANNEL_0 0:0 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_1 1:1 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_1_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_2 2:2 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_2_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_3 3:3 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_3_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_4 4:4 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_4_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_5 5:5 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_5_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_6 6:6 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_6_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_7 7:7 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_7_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_8 8:8 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_8_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_8_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_9 9:9 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_9_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_9_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_10 10:10 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_10_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_10_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_11 11:11 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_11_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_11_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_12 12:12 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_12_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_12_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_13 13:13 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_13_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_13_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_14 14:14 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_14_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_14_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_DMA_CHANNEL_15 15:15 /* RWIVF */ -#define NV_PFIFO_DMA_CHANNEL_15_NOT_PENDING 0x00000000 /* RWI-V */ -#define NV_PFIFO_DMA_CHANNEL_15_PENDING 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE 0x0000250C /* RW-4R */ -#define NV_PFIFO_SIZE_CHANNEL_0 0:0 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_1 1:1 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_2 2:2 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_3 3:3 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_4 4:4 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_5 5:5 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_6 6:6 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_7 7:7 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_8 8:8 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_8_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_8_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_9 9:9 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_9_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_9_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_10 10:10 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_10_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_10_512_BYTES 0x00000001 /* RW--V */ -#define NV_PFIFO_SIZE_CHANNEL_11 11:11 /* RWIVF */ -#define NV_PFIFO_SIZE_CHANNEL_11_124_BYTES 0x00000000 /* RWI-V */ -#define NV_PFIFO_SIZE_CHANNEL_11_512_BYTES 0x00000001 /* RW--V */ -#defin |