diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2005-12-09 19:04:18 +0100 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-01-09 14:53:21 +1100 |
| commit | 38307341af3a0be8ec5319756361b51ac29dffc7 (patch) | |
| tree | 082fae758ea5cc5e4376e7c9e0f3a6b479d59266 | |
| parent | 462c853eb574bc7843d9c56e84aca129aaa8e018 (diff) | |
[PATCH] spufs: clear dsisr on CLASS1[Mf] exception
Because of always clearing DSISR at spu class 1 interrupt handler,
kernel may lose Class1[Mf] interrupt.
Signed-off-by: Masato Noguchi <Masato.Noguchi@jp.sony.com>
Signed-off-by: Geoff Levand <geoff.levand@am.sony.com>
Signed-off-by: Arnd Bergmann <arndb@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
| -rw-r--r-- | arch/powerpc/platforms/cell/spu_base.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index f9da79eb3db..3a5302151e0 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c @@ -240,7 +240,8 @@ spu_irq_class_1(int irq, void *data, struct pt_regs *regs) stat = in_be64(&spu->priv1->int_stat_class1_RW) & mask; dar = in_be64(&spu->priv1->mfc_dar_RW); dsisr = in_be64(&spu->priv1->mfc_dsisr_RW); - out_be64(&spu->priv1->mfc_dsisr_RW, 0UL); + if (stat & 2) /* mapping fault */ + out_be64(&spu->priv1->mfc_dsisr_RW, 0UL); out_be64(&spu->priv1->int_stat_class1_RW, stat); spin_unlock(&spu->register_lock); |