diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2013-02-04 10:21:32 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2013-02-08 11:15:00 +0000 |
| commit | ff1ce0571eb98b21f5a9221b2fdc3bd010840b1a (patch) | |
| tree | 5e878eb9d2717b749691e4c52c20be8487aa2fc5 | |
| parent | 9ee417c07479b9a87d0808dd3c8b4ce3925983f1 (diff) | |
regulator: anatop: improve precision of delay time
For cpufreq example, it takes 13 steps (25 mV for one step) to increase
vddcore from 0.95 V to 1.275 V, and the time of 64 clock cycles at
24 MHz for one step is ~2.67 uS, so the total delay time would be
~34.71 uS. But the current calculation in the driver gives 39 uS.
Change the formula to have the addition of 1 be the last step, so that
we can get a more precise delay time. For example above, the new
formula will give 35 uS.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
| -rw-r--r-- | drivers/regulator/anatop-regulator.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c index 0df9c6a9760..0d4a8ccbb53 100644 --- a/drivers/regulator/anatop-regulator.c +++ b/drivers/regulator/anatop-regulator.c @@ -80,8 +80,8 @@ static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg, regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val); val = (val >> anatop_reg->delay_bit_shift) & ((1 << anatop_reg->delay_bit_width) - 1); - ret = (new_sel - old_sel) * ((LDO_RAMP_UP_UNIT_IN_CYCLES << - val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1); + ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES << + val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1; } return ret; |