MIPS: PNX8550: Remove support for SOC and JBS and STB810 boards.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

36 files changed, 5 insertions, 2882 deletions

diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 91b9d69f465..c7ea3a08c72 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -20,7 +20,6 @@ platforms += mti-sead3
 platforms += netlogic
 platforms += pmc-sierra
 platforms += pnx833x
-platforms += pnx8550
 platforms += powertv
 platforms += rb532
 platforms += sgi-ip22
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1110cd718ff..6b1c33b65d1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -385,16 +385,6 @@ config NXP_STB225
 	help
 	 Support for NXP Semiconductors STB225 Development Board.
 
-config PNX8550_JBS
-	bool "NXP PNX8550 based JBS board"
-	select PNX8550
-	select SYS_SUPPORTS_LITTLE_ENDIAN
-
-config PNX8550_STB810
-	bool "NXP PNX8550 based STB810 board"
-	select PNX8550
-	select SYS_SUPPORTS_LITTLE_ENDIAN
-
 config PMC_MSP
 	bool "PMC-Sierra MSP chipsets"
 	depends on EXPERIMENTAL
@@ -1113,19 +1103,6 @@ config SOC_PNX8335
 	bool
 	select SOC_PNX833X
 
-config PNX8550
-	bool
-	select SOC_PNX8550
-
-config SOC_PNX8550
-	bool
-	select DMA_NONCOHERENT
-	select HW_HAS_PCI
-	select SYS_HAS_CPU_MIPS32_R1
-	select SYS_HAS_EARLY_PRINTK
-	select SYS_SUPPORTS_32BIT_KERNEL
-	select GENERIC_GPIO
-
 config SWAP_IO_SPACE
 	bool
 
diff --git a/arch/mips/configs/pnx8550_jbs_defconfig b/arch/mips/configs/pnx8550_jbs_defconfig
deleted file mode 100644
index 1d1f2067f3e..00000000000
--- a/arch/mips/configs/pnx8550_jbs_defconfig
+++ /dev/null
@@ -1,98 +0,0 @@
-CONFIG_PNX8550_JBS=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_PCI=y
-CONFIG_PM=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_TCP_MD5SIG=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SGI_IOC4=m
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_BLK_DEV_OFFBOARD=y
-CONFIG_BLK_DEV_GENERIC=y
-CONFIG_BLK_DEV_HPT366=y
-CONFIG_BLK_DEV_IT8213=m
-CONFIG_BLK_DEV_TC86C001=m
-CONFIG_SCSI=y
-CONFIG_SCSI_TGT=m
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_SCSI_FC_ATTRS=y
-CONFIG_ISCSI_TCP=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_NET_PCI=y
-CONFIG_8139TOO=y
-# CONFIG_8139TOO_PIO is not set
-CONFIG_8139TOO_TUNE_TWISTER=y
-CONFIG_8139TOO_8129=y
-CONFIG_CHELSIO_T3=m
-CONFIG_NETXEN_NIC=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIAL_PNX8XXX=y
-CONFIG_SERIAL_PNX8XXX_CONSOLE=y
-CONFIG_HW_RANDOM=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_ISD200=y
-CONFIG_USB_STORAGE_USBAT=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_DLM=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SLAB=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRC_CCITT=m
diff --git a/arch/mips/configs/pnx8550_stb810_defconfig b/arch/mips/configs/pnx8550_stb810_defconfig
deleted file mode 100644
index 15c66a571f9..00000000000
--- a/arch/mips/configs/pnx8550_stb810_defconfig
+++ /dev/null
@@ -1,92 +0,0 @@
-CONFIG_PNX8550_STB810=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_HOTPLUG is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_PCI=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_MIGRATE=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDECD=m
-CONFIG_IDE_GENERIC=y
-CONFIG_BLK_DEV_OFFBOARD=y
-CONFIG_BLK_DEV_GENERIC=y
-CONFIG_BLK_DEV_HPT366=y
-CONFIG_BLK_DEV_IT8213=m
-CONFIG_BLK_DEV_TC86C001=m
-CONFIG_SCSI=y
-CONFIG_SCSI_TGT=m
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_ISCSI_TCP=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_NET_PCI=y
-CONFIG_NATSEMI=y
-CONFIG_CHELSIO_T3=m
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO_I8042 is not set
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
-CONFIG_HW_RANDOM=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_ISD200=y
-CONFIG_USB_STORAGE_USBAT=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_DLM=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_HEADERS_CHECK=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SLAB=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_CAMELLIA=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRC_CCITT=m
diff --git a/arch/mips/include/asm/mach-pnx8550/cm.h b/arch/mips/include/asm/mach-pnx8550/cm.h
deleted file mode 100644
index bb0a56c7d01..00000000000
--- a/arch/mips/include/asm/mach-pnx8550/cm.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   Clock module specific definitions
- *
- * Author: source@mvista.com
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-
-#ifndef __PNX8550_CM_H
-#define __PNX8550_CM_H
-
-#define PNX8550_CM_BASE	0xBBE47000
-
-#define PNX8550_CM_PLL0_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
-#define PNX8550_CM_PLL1_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
-#define PNX8550_CM_PLL2_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
-#define PNX8550_CM_PLL3_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
-
-// Table not complete.....
-
-#define PNX8550_CM_PLL_BLOCKED_MASK     0x80000000
-#define PNX8550_CM_PLL_LOCK_MASK        0x40000000
-#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
-#define PNX8550_CM_PLL_N_MASK           0x01ff0000
-#define PNX8550_CM_PLL_M_MASK           0x00003f00
-#define PNX8550_CM_PLL_P_MASK           0x0000000c
-#define PNX8550_CM_PLL_PD_MASK          0x00000002
-
-
-#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/glb.h b/arch/mips/include/asm/mach-pnx8550/glb.h
deleted file mode 100644
index 07aa85e609b..00000000000
--- a/arch/mips/include/asm/mach-pnx8550/glb.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   PNX8550 global definitions
- *
- * Author: source@mvista.com
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-
-#ifndef __PNX8550_GLB_H
-#define __PNX8550_GLB_H
-
-#define PNX8550_GLB1_BASE	0xBBE63000
-#define PNX8550_GLB2_BASE	0xBBE4d000
-#define PNX8550_RESET_BASE      0xBBE60000
-
-/* PCI Inta Output Enable Registers */
-#define PNX8550_GLB2_ENAB_INTA_O	*(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
-
-/* Bit 1:Enable DAC Powerdown
-     0:DACs are enabled and are working normally
-     1:DACs are powerdown
-*/
-#define PNX8550_GLB_DAC_PD      0x2
-/*   Bit 0:Enable of PCI inta output
-     0 = Disable PCI inta output
-     1 = Enable PCI inta output
-*/
-#define PNX8550_GLB_ENABLE_INTA_O 0x1
-
-/* PCI Direct Mappings */
-#define PNX8550_PCIMEM	        0x12000000
-#define PNX8550_PCIMEM_SIZE	0x08000000
-#define PNX8550_PCIIO	        0x1c000000
-#define PNX8550_PCIIO_SIZE	0x02000000	/* 32M */
-
-#define PNX8550_PORT_BASE	KSEG1
-
-// GPIO def
-#define PNX8550_GPIO_BASE	0x1Be00000
-
-#define PNX8550_GPIO_DIRQ0	 (PNX8550_GPIO_BASE + 0x104500)
-#define PNX8550_GPIO_MC1         (PNX8550_GPIO_BASE + 0x104004)
-#define PNX8550_GPIO_MC_31_BIT   30
-#define PNX8550_GPIO_MC_30_BIT   28
-#define PNX8550_GPIO_MC_29_BIT   26
-#define PNX8550_GPIO_MC_28_BIT   24
-#define PNX8550_GPIO_MC_27_BIT   22
-#define PNX8550_GPIO_MC_26_BIT   20
-#define PNX8550_GPIO_MC_25_BIT   18
-#define PNX8550_GPIO_MC_24_BIT   16
-#define PNX8550_GPIO_MC_23_BIT   14
-#define PNX8550_GPIO_MC_22_BIT   12
-#define PNX8550_GPIO_MC_21_BIT   10
-#define PNX8550_GPIO_MC_20_BIT   8
-#define PNX8550_GPIO_MC_19_BIT   6
-#define PNX8550_GPIO_MC_18_BIT   4
-#define PNX8550_GPIO_MC_17_BIT   2
-#define PNX8550_GPIO_MC_16_BIT   0
-
-#define PNX8550_GPIO_MODE_PRIMOP    0x1
-#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
-#define PNX8550_GPIO_MODE_OPENDR    0x3
-
-// RESET module
-#define PNX8550_RST_CTL             *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
-#define PNX8550_RST_CAUSE           *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
-#define PNX8550_RST_EN_WATCHDOG     *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
-
-#define PNX8550_RST_REL_MIPS_RST_N     0x8
-#define PNX8550_RST_DO_SW_RST          0x4
-#define PNX8550_RST_REL_SYS_RST_OUT    0x2
-#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
-#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/int.h b/arch/mips/include/asm/mach-pnx8550/int.h
deleted file mode 100644
index 0e0668b524f..00000000000
--- a/arch/mips/include/asm/mach-pnx8550/int.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   Interrupt specific definitions
- *
- * Author: source@mvista.com
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-
-#ifndef __PNX8550_INT_H
-#define __PNX8550_INT_H
-
-#define PNX8550_GIC_BASE	0xBBE3E000
-
-#define PNX8550_GIC_PRIMASK_0	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
-#define PNX8550_GIC_PRIMASK_1	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
-#define PNX8550_GIC_VECTOR_0	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
-#define PNX8550_GIC_VECTOR_1	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
-#define PNX8550_GIC_PEND_1_31	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
-#define PNX8550_GIC_PEND_32_63	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
-#define PNX8550_GIC_PEND_64_70	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
-#define PNX8550_GIC_FEATURES	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
-#define PNX8550_GIC_REQ(x)	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
-#define PNX8550_GIC_MOD_ID	*(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
-
-// cp0 is two software + six hw exceptions
-#define PNX8550_INT_CP0_TOTINT	8
-#define PNX8550_INT_CP0_MIN	0
-#define PNX8550_INT_CP0_MAX	(PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
-
-#define MIPS_CPU_GIC_IRQ        2
-#define MIPS_CPU_TIMER_IRQ      7
-
-// GIC are 71 exceptions connected to cp0's first hardware exception
-#define PNX8550_INT_GIC_TOTINT	71
-#define PNX8550_INT_GIC_MIN	(PNX8550_INT_CP0_MAX+1)
-#define PNX8550_INT_GIC_MAX	(PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
-
-#define PNX8550_INT_UNDEF              (PNX8550_INT_GIC_MIN+0)
-#define PNX8550_INT_IPC_TARGET0_MIPS   (PNX8550_INT_GIC_MIN+1)
-#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
-#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
-#define PNX8550_INT_RESERVED_4         (PNX8550_INT_GIC_MIN+4)
-#define PNX8550_INT_USB                (PNX8550_INT_GIC_MIN+5)
-#define PNX8550_INT_GPIO_EQ1           (PNX8550_INT_GIC_MIN+6)
-#define PNX8550_INT_GPIO_EQ2           (PNX8550_INT_GIC_MIN+7)
-#define PNX8550_INT_GPIO_EQ3           (PNX8550_INT_GIC_MIN+8)
-#define PNX8550_INT_GPIO_EQ4           (PNX8550_INT_GIC_MIN+9)
-
-#define PNX8550_INT_GPIO_EQ5           (PNX8550_INT_GIC_MIN+10)
-#define PNX8550_INT_GPIO_EQ6           (PNX8550_INT_GIC_MIN+11)
-#define PNX8550_INT_RESERVED_12        (PNX8550_INT_GIC_MIN+12)
-#define PNX8550_INT_QVCP1              (PNX8550_INT_GIC_MIN+13)
-#define PNX8550_INT_QVCP2              (PNX8550_INT_GIC_MIN+14)
-#define PNX8550_INT_I2C1               (PNX8550_INT_GIC_MIN+15)
-#define PNX8550_INT_I2C2               (PNX8550_INT_GIC_MIN+16)
-#define PNX8550_INT_ISO_UART1          (PNX8550_INT_GIC_MIN+17)
-#define PNX8550_INT_ISO_UART2          (PNX8550_INT_GIC_MIN+18)
-#define PNX8550_INT_UART1              (PNX8550_INT_GIC_MIN+19)
-
-#define PNX8550_INT_UART2              (PNX8550_INT_GIC_MIN+20)
-#define PNX8550_INT_QNTR               (PNX8550_INT_GIC_MIN+21)
-#define PNX8550_INT_RESERVED22         (PNX8550_INT_GIC_MIN+22)
-#define PNX8550_INT_T_DSC              (PNX8550_INT_GIC_MIN+23)
-#define PNX8550_INT_M_DSC              (PNX8550_INT_GIC_MIN+24)
-#define PNX8550_INT_RESERVED25         (PNX8550_INT_GIC_MIN+25)
-#define PNX8550_INT_2D_DRAW_ENG        (PNX8550_INT_GIC_MIN+26)
-#define PNX8550_INT_MEM_BASED_SCALAR1  (PNX8550_INT_GIC_MIN+27)
-#define PNX8550_INT_VIDEO_MPEG         (PNX8550_INT_GIC_MIN+28)
-#define PNX8550_INT_VIDEO_INPUT_P1     (PNX8550_INT_GIC_MIN+29)
-
-#define PNX8550_INT_VIDEO_INPUT_P2     (PNX8550_INT_GIC_MIN+30)
-#define PNX8550_INT_SPDI1              (PNX8550_INT_GIC_MIN+31)
-#define PNX8550_INT_SPDO               (PNX8550_INT_GIC_MIN+32)
-#define PNX8550_INT_AUDIO_INPUT1       (PNX8550_INT_GIC_MIN+33)
-#define PNX8550_INT_AUDIO_OUTPUT1      (PNX8550_INT_GIC_MIN+34)
-#define PNX8550_INT_AUDIO_INPUT2       (PNX8550_INT_GIC_MIN+35)
-#define PNX8550_INT_AUDIO_OUTPUT2      (PNX8550_INT_GIC_MIN+36)
-#define PNX8550_INT_MEMBASED_SCALAR2   (PNX8550_INT_GIC_MIN+37)
-#define PNX8550_INT_VPK                (PNX8550_INT_GIC_MIN+38)
-#define PNX8550_INT_MPEG1_MIPS         (PNX8550_INT_GIC_MIN+39)
-
-#define PNX8550_INT_MPEG1_TM           (PNX8550_INT_GIC_MIN+40)
-#define PNX8550_INT_MPEG2_MIPS         (PNX8550_INT_GIC_MIN+41)
-#define PNX8550_INT_MPEG2_TM           (PNX8550_INT_GIC_MIN+42)
-#define PNX8550_INT_TS_DMA             (PNX8550_INT_GIC_MIN+43)
-#define PNX8550_INT_EDMA               (PNX8550_INT_GIC_MIN+44)
-#define PNX8550_INT_TM_DEBUG1          (PNX8550_INT_GIC_MIN+45)
-#define PNX8550_INT_TM_DEBUG2          (PNX8550_INT_GIC_MIN+46)
-#define PNX8550_INT_PCI_INTA           (PNX8550_INT_GIC_MIN+47)
-#define PNX8550_INT_CLOCK_MODULE       (PNX8550_INT_GIC_MIN+48)
-#define PNX8550_INT_PCI_XIO_INTA_PCI   (PNX8550_INT_GIC_MIN+49)
-
-#define PNX8550_INT_PCI_XIO_INTB_DMA   (PNX8550_INT_GIC_MIN+50)
-#define PNX8550_INT_PCI_XIO_INTC_GPPM  (PNX8550_INT_GIC_MIN+51)
-#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
-#define PNX8550_INT_DVD_CSS            (PNX8550_INT_GIC_MIN+53)
-#define PNX8550_INT_VLD                (PNX8550_INT_GIC_MIN+54)
-#define PNX8550_INT_GPIO_TSU_7_0       (PNX8550_INT_GIC_MIN+55)
-#define PNX8550_INT_GPIO_TSU_15_8      (PNX8550_INT_GIC_MIN+56)
-#define PNX8550_INT_GPIO_CTU_IR        (PNX8550_INT_GIC_MIN+57)
-#define PNX8550_INT_GPIO0              (PNX8550_INT_GIC_MIN+58)
-#define PNX8550_INT_GPIO1              (PNX8550_INT_GIC_MIN+59)
-
-#define PNX8550_INT_GPIO2              (PNX8550_INT_GIC_MIN+60)
-#define PNX8550_INT_GPIO3              (PNX8550_INT_GIC_MIN+61)
-#define PNX8550_INT_GPIO4              (PNX8550_INT_GIC_MIN+62)
-#define PNX8550_INT_GPIO5              (PNX8550_INT_GIC_MIN+63)
-#define PNX8550_INT_GPIO6              (PNX8550_INT_GIC_MIN+64)
-#define PNX8550_INT_GPIO7              (PNX8550_INT_GIC_MIN+65)
-#define PNX8550_INT_PMAN_SECURITY      (PNX8550_INT_GIC_MIN+66)
-#define PNX8550_INT_I2C3               (PNX8550_INT_GIC_MIN+67)
-#define PNX8550_INT_RESERVED_68        (PNX8550_INT_GIC_MIN+68)
-#define PNX8550_INT_SPDI2              (PNX8550_INT_GIC_MIN+69)
-
-#define PNX8550_INT_I2C4               (PNX8550_INT_GIC_MIN+70)
-
-// Timer are 3 exceptions connected to cp0's 7th hardware exception
-#define PNX8550_INT_TIMER_TOTINT       3
-#define PNX8550_INT_TIMER_MIN	       (PNX8550_INT_GIC_MAX+1)
-#define PNX8550_INT_TIMER_MAX          (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
-
-#define PNX8550_INT_TIMER1             (PNX8550_INT_TIMER_MIN+0)
-#define PNX8550_INT_TIMER2             (PNX8550_INT_TIMER_MIN+1)
-#define PNX8550_INT_TIMER3             (PNX8550_INT_TIMER_MIN+2)
-#define PNX8550_INT_WATCHDOG           PNX8550_INT_TIMER3
-
-#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h b/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h
deleted file mode 100644
index bdde00c9199..00000000000
--- a/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005 Embedded Alley Solutions, Inc
- */
-#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
-#define __ASM_MACH_KERNEL_ENTRY_INIT_H
-
-#include <asm/cacheops.h>
-#include <asm/addrspace.h>
-
-#define CO_CONFIGPR_VALID  0x3F1F41FF    /* valid bits to write to ConfigPR */
-#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
-#define CACHE_OPC      0xBC000000  /* MIPS cache instruction opcode */
-#define ICACHE_LINE_SIZE        32      /* Instruction cache line size bytes */
-#define DCACHE_LINE_SIZE        32      /* Data cache line size in bytes */
-
-#define ICACHE_SET_COUNT        256     /* Instruction cache set count */
-#define DCACHE_SET_COUNT        128     /* Data cache set count */
-
-#define ICACHE_SET_SIZE         (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
-#define DCACHE_SET_SIZE         (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
-
-	.macro	kernel_entry_setup
-	.set	push
-	.set	noreorder
-	/*
-	 * PNX8550 entry point, when running a non compressed
-	 * kernel. When loading a zImage, the head.S code in
-	 * arch/mips/zboot/pnx8550 will init the caches and,
-	 * decompress the kernel, and branch to kernel_entry.
-		 */
-cache_begin:	li	t0, (1<<28)
-	mtc0	t0, CP0_STATUS /* cp0 usable */
-	HAZARD_CP0
-
-	mtc0 	zero, CP0_CAUSE
-	HAZARD_CP0
-
-
-	/* Set static virtual to phys address translation and TLB disabled */
-	mfc0 	t0, CP0_CONFIG, 7
-	HAZARD_CP0
-
-	and	t0, ~((1<<19) | (1<<20))     /* TLB/MAP cleared */
-	mtc0	t0, CP0_CONFIG, 7
-	HAZARD_CP0
-
-	/* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
-
-	init_icache
-	nop
-	init_dcache
-	nop
-
-	cachePr4450ICReset
-	nop
-
-	cachePr4450DCReset
-	nop
-
-	/* read ConfigPR into t0 */
-	mfc0	t0, CP0_CONFIG, 7
-	HAZARD_CP0
-
-	/*  enable the TLB */
-	or      t0, (1<<19)
-
-	/* disable the ICACHE: at least 10x slower */
-	/* or      t0, (1<<26) */
-
-	/* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set  */
-	/* or      t0, (1<<27) */
-
-	and	t0, CO_CONFIGPR_VALID
-
-	/* enable TLB. */
-	mtc0	t0, CP0_CONFIG, 7
-	HAZARD_CP0
-cache_end:
-	/* Setup CMEM_0 to MMIO address space, 2MB */
-	lui    t0, 0x1BE0
-	addi   t0, t0, 0x3
-	mtc0   $8, $22, 4
-	nop
-
-	/* Setup CMEM_1, 128MB */
-	lui    t0, 0x1000
-	addi   t0, t0, 0xf
-	mtc0   $8, $22, 5
-	nop
-
-
-	/* Setup CMEM_2, 32MB */
-	lui    t0, 0x1C00
-	addi   t0, t0, 0xb
-	mtc0   $8, $22, 6
-	nop
-
-	/* Setup CMEM_3, 0MB */
-	lui    t0, 0x0
-	addi   t0, t0, 0x0
-	mtc0   $8, $22, 7
-	nop
-
-	/* Enable cache */
-	mfc0	t0, CP0_CONFIG
-	HAZARD_CP0
-	and	t0, t0, 0xFFFFFFF8
-	or	t0, t0, 3
-	mtc0	t0, CP0_CONFIG
-	HAZARD_CP0
-	.set	pop
-	.endm
-
-	.macro	init_icache
-	.set	push
-	.set	noreorder
-
-	/* Get Cache Configuration */
-	mfc0	t3, CP0_CONFIG, 1
-	HAZARD_CP0
-
-	/* get cache Line size */
-
-	srl   t1, t3, 19   /* C0_CONFIGPR_IL_SHIFT */
-	andi  t1, t1, 0x7  /* C0_CONFIGPR_IL_MASK */
-	beq   t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
-	nop
-	addiu t0, t1, 1
-	ori   t1, zero, 1
-	sllv  t1, t1, t0
-
-	/* get max cache Index */
-	srl   t2, t3, 22  /* C0_CONFIGPR_IS_SHIFT */
-	andi  t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
-	addiu t0, t2, 6
-	ori   t2, zero, 1
-	sllv  t2, t2, t0
-
-	/* get max cache way */
-	srl   t3, t3, 16  /* C0_CONFIGPR_IA_SHIFT */
-	andi  t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
-	addiu t3, t3, 1
-
-	/* total no of cache lines */
-	multu t2, t3             /* max index * max way */
-	mflo  t2
-	addiu t2, t2, -1
-
-	move  t0, zero
-pr4450_next_instruction_cache_set:
-	cache  Index_Invalidate_I, 0(t0)
-	addu  t0, t0, t1         /* add bytes in a line */
-	bne   t2, zero, pr4450_next_instruction_cache_set
-	addiu t2, t2, -1   /* reduce no of lines to invalidate by one */
-pr4450_instr_cache_invalidated:
-	.set	pop
-	.endm
-
-	.macro	init_dcache
-	.set	push
-	.set	noreorder
-	move t1, zero
-
-	/* Store Tag Information */
-	mtc0	zero, CP0_TAGLO, 0
-	HAZARD_CP0
-
-	mtc0	zero, CP0_TAGHI, 0
-	HAZARD_CP0
-
-	/* Cache size is 16384 = 512 lines x 32 bytes per line */
-	or       t2, zero, (128*4)-1  /* 512 lines  */
-	/* Invalidate all lines */
-2:
-	cache Index_Store_Tag_D, 0(t1)
-	addiu    t2, t2, -1
-	bne      t2, zero, 2b
-	addiu    t1, t1, 32        /* 32 bytes in a line */
-	.set pop
-	.endm
-
-	.macro	cachePr4450ICReset
-	.set	push
-	.set	noreorder
-
-	/* Save CP0 status reg on entry; */
-	/* disable interrupts during cache reset */
-	mfc0    t0, CP0_STATUS      /* T0 = interrupt status on entry */
-	HAZARD_CP0
-
-	mtc0    zero, CP0_STATUS   /* disable CPU interrupts */
-	HAZARD_CP0
-
-	or      t1, zero, zero              /* T1 = starting cache index (0) */
-	ori     t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
-
-	icache_invd_loop:
-	/* 9 == register t1 */
-	.word   CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
-		(0 * ICACHE_SET_SIZE)  /* invalidate inst cache WAY0 */
-	.word   CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
-		(1 * ICACHE_SET_SIZE)  /* invalidate inst cache WAY1 */
-
-	addiu   t1, t1, ICACHE_LINE_SIZE    /* T1 = next cache line index */
-	bne     t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
-	addiu   t2, t2, -1        /* decrement T2 set cnt (delay slot) */
-
-	/* Initialize the latches in the instruction cache tag */
-	/* that drive the way selection tri-state bus drivers, by doing a */
-	/* dummy load while the instruction cache is still disabled. */
-	/* TODO: Is this needed ? */
-	la      t1, KSEG0            /* T1 = cached memory base address */
-	lw      zero, 0x0000(t1)      /* (dummy read of first memory word) */
-
-	mtc0    t0, CP0_STATUS        /* restore interrupt status on entry */
-	HAZARD_CP0
-	.set	pop
-	.endm
-
-	.macro	cachePr4450DCReset
-	.set	push
-	.set	noreorder
-	mfc0    t0, CP0_STATUS           /* T0 = interrupt status on entry */
-	HAZARD_CP0
-	mtc0    zero, CP0_STATUS         /* disable CPU interrupts */
-	HAZARD_CP0
-
-	/* Writeback/invalidate entire data cache sets/ways/lines */
-	or      t1, zero, zero              /* T1 = starting cache index (0) */
-	ori     t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
-
-	dcache_wbinvd_loop:
-	/* 9 == register t1 */
-	.word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
-		(0 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY0 */
-	.word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
-		(1 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY1 */
-	.word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
-		(2 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY2 */
-	.word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
-		(3 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY3 */