diff options
| author | Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> | 2011-07-11 10:15:45 +0900 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-07-22 09:06:41 -0700 |
| commit | 0cab0841dc1400f633a7e1ac1e448518692f927a (patch) | |
| tree | 2b4ba002d6d4ee69ad351a2bcf7f9c484f696d2f | |
| parent | 9b373ed18f745bddf4288f1ec4a51fe822b8610a (diff) | |
PCI: pciehp: change wait time for valid configuration access
Naoki Yanagimoto reported that configuration read on some hot-added
PCIe device returns invalid value. This patch fixes this problem.
According to the PCIe spec, software must wait for at least 1 second
to judge if the hot-added device is broken after Data Link Layer State
Changed Event. This patch changes pciehp driver to wait for 1 second
after the Data Link Layer State Changed Event is detected before
initiating a configuration access instead of 100 ms.
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Tested-by: Naoki Yanagimoto <yanagimoto@np.css.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| -rw-r--r-- | drivers/pci/hotplug/pciehp_ctrl.c | 3 | ||||
| -rw-r--r-- | drivers/pci/hotplug/pciehp_hpc.c | 11 |
2 files changed, 5 insertions, 9 deletions
diff --git a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c index 085dbb5fc16..1e9c9aacc3a 100644 --- a/drivers/pci/hotplug/pciehp_ctrl.c +++ b/drivers/pci/hotplug/pciehp_ctrl.c @@ -213,6 +213,9 @@ static int board_added(struct slot *p_slot) goto err_exit; } + /* Wait for 1 second after checking link training status */ + msleep(1000); + /* Check for a power fault */ if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) { ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot)); diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 50a23da5d24..96dc4734e4a 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -275,16 +275,9 @@ int pciehp_check_link_status(struct controller *ctrl) * hot-plug capable downstream port. But old controller might * not implement it. In this case, we wait for 1000 ms. */ - if (ctrl->link_active_reporting){ - /* Wait for Data Link Layer Link Active bit to be set */ + if (ctrl->link_active_reporting) pcie_wait_link_active(ctrl); - /* - * We must wait for 100 ms after the Data Link Layer - * Link Active bit reads 1b before initiating a - * configuration access to the hot added device. - */ - msleep(100); - } else + else msleep(1000); retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); |